Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Dv/Dt Controlled, Tri-State Gpi Driver Using Advanced Transistor Technology

IP.com Disclosure Number: IPCOM000061771D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+4]

Abstract

This article describes an inverting, tri-state, push-pull off-chip driver circuit, with controlled transition rates, that will interface with a RAM (random-access memory) sense amplifier output. The rising and falling transition rates of the driver circuit are controlled to less than 1.0 volt per nanosecond in both logical operation and when the driver is exiting the high impedance state. This is accomplished by use of the structures labeled C1 and C2 in the diagram, which are chip-embedded 2 Kohm-per-square resistor beds, wired so as to provide capacitance at the transition controlling nodes. Devices TD1 (transistor), S2 (Schottky barrier diode), and TD3 (transistor) provide for active discharge of the transistor T3 base, thereby eliminating any excess power supply drain current during a rising output transition.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Dv/Dt Controlled, Tri-State Gpi Driver Using Advanced Transistor Technology

This article describes an inverting, tri-state, push-pull off-chip driver circuit, with controlled transition rates, that will interface with a RAM (random-access memory) sense amplifier output. The rising and falling transition rates of the driver circuit are controlled to less than 1.0 volt per nanosecond in both logical operation and when the driver is exiting the high impedance state. This is accomplished by use of the structures labeled C1 and C2 in the diagram, which are chip-embedded 2 Kohm-per-square resistor beds, wired so as to provide capacitance at the transition controlling nodes. Devices TD1 (transistor), S2 (Schottky barrier diode), and TD3 (transistor) provide for active discharge of the transistor T3 base, thereby eliminating any excess power supply drain current during a rising output transition. The input devices T1 (transistor), T1A (transistor) and T2A (transistor) are required so as to establish a compatible interface with the internal levels of the RAM sense amplifier.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]