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Technique for Performing Module-Level Automated Testing for CMOS Latch-Up

IP.com Disclosure Number: IPCOM000061773D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

McLean, JG: AUTHOR

Abstract

A technique is described whereby semiconductors which are fabricated using complementary metal-oxide silicon (CMOS) technology are automatically tested for latch-up susceptibility. The test is unique in that an automated tester used to detect latch-up characteristics of CMOS semiconductors has the ability to remove power from the semiconductor as soon as a latch is detected, so as not to destroy the semiconductor during the test. Furthermore, the technique allows rapid sequential testing at multiple pin locations without fear that damage to previously tested pin locations will affect results.

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Technique for Performing Module-Level Automated Testing for CMOS Latch-Up

A technique is described whereby semiconductors which are fabricated using complementary metal-oxide silicon (CMOS) technology are automatically tested for latch-up susceptibility. The test is unique in that an automated tester used to detect latch-up characteristics of CMOS semiconductors has the ability to remove power from the semiconductor as soon as a latch is detected, so as not to destroy the semiconductor during the test. Furthermore, the technique allows rapid sequential testing at multiple pin locations without fear that damage to previously tested pin locations will affect results. In the prior art, testing of latch- up susceptibility of CMOS semiconductors required laborious bench testing whereby DC current is applied to the semiconductor to determine the maximum current which may be injected and the maximum voltage reached before latch-up occurs. Errors were prevalent in the reading of current and voltages as well as having the test itself destroy the semiconductor. The technique described herein incorporates latch-up testing with other testing procedures using the SENTRY* Tester; however, other testers may easily incorporate the concept. The procedure may be called from a semiconductor test program as a macro routine, or it may be a stand-alone. The procedure, as shown in the flow chart, consists of six basic steps: 1. Initialization - the semiconductor pins to be tested are defined along with the incremental current value, voltage trigger value and the desired log-out options. The operator has the option of either inputting the information for interactive testing or incorporating the information directly into the test program. 2. Power up - the power-up sequence is performe...