Browse Prior Art Database

Method of Power On/Off Diskette Controller

IP.com Disclosure Number: IPCOM000061784D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Carson, MR: AUTHOR [+4]

Abstract

A CMOS diskette controller that is program compatible with the IBM Personal Computer (PC) diskette controller is not available. In building a battery-powered portable PC that is program compatible with the existing PC line, a NMOS diskette controller had to be used. To conserve battery power, this controller's power must be turned off when the diskette drives are not being accessed. A method is described to solve this problem without sacrificing program compatibility. The program never knows that power is being cycled on the diskette controller even if the program goes around the PC BIOS microcode. This method involves both microcode and hardware. The normal state of the diskette controller is power off.

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Method of Power On/Off Diskette Controller

A CMOS diskette controller that is program compatible with the IBM Personal Computer (PC) diskette controller is not available. In building a battery-powered portable PC that is program compatible with the existing PC line, a NMOS diskette controller had to be used. To conserve battery power, this controller's power must be turned off when the diskette drives are not being accessed. A method is described to solve this problem without sacrificing program compatibility. The program never knows that power is being cycled on the diskette controller even if the program goes around the PC BIOS microcode. This method involves both microcode and hardware. The normal state of the diskette controller is power off. When a program accesses one of the diskette controller ports with either a read or write I/O, a Non-Maskable Interrupt (NMI) is generated. This activates ROM microcode that powers on the controller and issues I/O commands to the controller to re-synchronize its state with the state of the diskette drives. This re-synchronization process consists of re-initializing diskette drive parameters kept by the controller as well as re-establishing the current head position of each drive that is attached to the controller. Once this has been done, the NMI microcode decrements the program return address on the stack by one, restores all registers, and returns to the program that issued the I/O instruction while the controller was in the off state. Since the return address was modified by one, the original IN or OUT I/O instruction is reissued to a powered on, updated controller. The controller power stays on until the diskette motor's transition to an off state. The hardware then powers off the controller. The hardware is designed so that switching from one drive motor to another does not power off the controller. This insures that there is no NMI generated and no performance degradation when doing copy operations between drives. In most microcode accesses to the diskette system, the diskette drive motors are turned on before the controller is accessed. Since a 500- millisecond delay is required for motor start-up before accessing the diskette drive, the controller power-up sequence is overlapped with this delay, adding no additional time to the diskette access. The hardware support for this function consists of the fol...