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Isolation of Fault(s) by Boolean Manipulation Program

IP.com Disclosure Number: IPCOM000061787D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Smith, GL: AUTHOR

Abstract

Means are provided for isolating a fault or faults in the absence of knowledge as to the failure mechanism. A Boolean manipulation program that is capable of solving the tautology problem is used to isolate any part that might possibly cause the failure by itself. Such isolation is unique in that a part is identified as a candidate for replacement if any conceivable combination of faults in the part could cause the failure state. Thus, a part becomes a candidate for replacement if it could have caused the failure through a single internal fault, a double internal fault, or any set of multiple internal faults. Furthermore, these faults may be any type of DC fault.

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Isolation of Fault(s) by Boolean Manipulation Program

Means are provided for isolating a fault or faults in the absence of knowledge as to the failure mechanism. A Boolean manipulation program that is capable of solving the tautology problem is used to isolate any part that might possibly cause the failure by itself. Such isolation is unique in that a part is identified as a candidate for replacement if any conceivable combination of faults in the part could cause the failure state. Thus, a part becomes a candidate for replacement if it could have caused the failure through a single internal fault, a double internal fault, or any set of multiple internal faults. Furthermore, these faults may be any type of DC fault. It is not possible, as in fault simulation, to fail to identify a part as a candidate for replacement through failure to include the proper set of faults in a fault list. For the following, it is assumed that some sort of boundary is drawn within the logic and connections, and that one side of the boundary is to be ccalled an "island". Useful examples (Fig. 1) of the islands are an entire chip, everything outside a given chip, or an area of a chip - including circuits and wires. It is assumed that the pattern of the failure (i.e., the state of the storage elements in the cycle immediately prior to the failure), the identity of the capturing storage elements (those that detected the failure), the resulting state of the storage elements after the pattern has been clocked (the "failure state"), and a logic block model of the hardware are all available when a failure is detected. The model represents combinational circuits and connections bounded by storage elements of the hardware under test (or the tester). Let us assume for now that our purpose is to determine whether a given island can be a possible cause of a failure by itself. The following steps are taken to create an isolation model: 1. A unique variable is associated with each boundary point of the island in the hardware model. The hardware model is then cut at the island boundary and that portion of the model that describes the island is discarded. 2. The state of the hardware immediately prior to failure is applied to the remaining inputs of the model and propagated forward. All blocks with constant output values are dropped. 3. The outputs of the remaining model that correspond to capturing storage elements are identified. 4. The following two steps are repeated until execution of a step results in the flagging of no additional blocks: A. Flag...