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Efficient Two-Mode Fully Testable LSSD Clock Generator Circuit

IP.com Disclosure Number: IPCOM000061807D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Gramann, PA: AUTHOR

Abstract

A common method used to generate nonoverlapping clocks requires two oscillator primary inputs to be fully testable. AS shown and described in the IBM Technical Disclosure Bulletin 28, 1612 (September 1985), a single oscillator primary input is used in a fully testable clock generation circuit, but this circuit requires two additional test inputs. Thus, the advantage of only one oscillator input requires five primary inputs in comparison with four in the previous method. The circuit in this disclosure, as shown in Fig. 1, overcomes the disadvantage of the previous circuit by reducing the number of primary inputs to four while remaining fully testable for stuck fault conditions.

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Efficient Two-Mode Fully Testable LSSD Clock Generator Circuit

A common method used to generate nonoverlapping clocks requires two oscillator primary inputs to be fully testable. AS shown and described in the IBM Technical Disclosure Bulletin 28, 1612 (September 1985), a single oscillator primary input is used in a fully testable clock generation circuit, but this circuit requires two additional test inputs. Thus, the advantage of only one oscillator input requires five primary inputs in comparison with four in the previous method. The circuit in this disclosure, as shown in Fig. 1, overcomes the disadvantage of the previous circuit by reducing the number of primary inputs to four while remaining fully testable for stuck fault conditions. This circuit can be run in either of two modes to accommodate both a chip designer's preference, as well as technologies with differing level sensitive scan design (LSSD) clock requirements. In normal operation, the -B Clock Control input is low and the +C Clock Control input is high. An oscillator signal is applied to input A while input A1 is held at either a high or low level to select one of the two operating modes. If A1 is low (Fig. 2), the B and C clock inputs will have longer clock pulses that are close together. If A1 is high (Fig. 3), the B and C clock outputs will have shorter clock pulses that are farther apart. If the optional delay block is included in the circuit, the clock pulses will be shorter with more time be...