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Self-Assisted Logic Testing

IP.com Disclosure Number: IPCOM000061812D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Klara, WS: AUTHOR [+4]

Abstract

During the manufacturing process for logic chips, a number of problems can occur that could make these chips defective. Some of these problems cause DC defects; testing methodologies for detection of these are widely used throughout the industry. However, some of these problems can cause AC defects. That is, the logic will function correctly, but slower than it should. Inexpensive testing methodologies for this case are not common. This article describes such a methodology, implemented by circuitry added to the logic chip to assist in testing itself. The diagram shown in Fig. 1 illustrates a way to design a logic chip so that AC testing can be performed using signals at a DC rate only, external to the chip. If not already present in the design, latches are added at the inputs (LI) and outputs (LO) of the chip.

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Self-Assisted Logic Testing

During the manufacturing process for logic chips, a number of problems can occur that could make these chips defective. Some of these problems cause DC defects; testing methodologies for detection of these are widely used throughout the industry. However, some of these problems can cause AC defects. That is, the logic will function correctly, but slower than it should. Inexpensive testing methodologies for this case are not common. This article describes such a methodology, implemented by circuitry added to the logic chip to assist in testing itself. The diagram shown in Fig. 1 illustrates a way to design a logic chip so that AC testing can be performed using signals at a DC rate only, external to the chip. If not already present in the design, latches are added at the inputs (LI) and outputs (LO) of the chip. The input pattern for the worst-case (WC) delay is determined, and the actual circuit delays to each output latch LO are calculated, with results as shown in Fig. 2. A recirculating loop, as shown in Fig. 3, is also added to the chip. Appropriate output taps from this loop are connected to the clock inputs to the LO latches. For example, the delay through the logic to output D2' is shown as 6.2 nanoseconds. If each state in the recirculating loop has a
1.0 NS delay, we would take the tap off the 7.0 NS point on the chain (C7). In the test operation, the RLF INH (Fig. 3) input would be set first to allow oscillation. By frequency...