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Multiple-Cycle Level Sensitive SCAN Design

IP.com Disclosure Number: IPCOM000061821D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR [+4]

Abstract

The present design reduces the overhead in the traditional Level Sensitive Scan Design (LSSD) by allowing a multiple cycle test operation between scan-in and scan-out operations. One extra pin and one AND gate are additionally provided to support the multiple cycle test operation. The traditional LSSD requires that all flip-flops and latches in one circuit macro be converted to scan registers. These registers are chained together and shift controlled by primary inputs and outputs. Tests are done by scanning (shifting) a set of test vectors into all registers, running one system clock cycle and scanning out all register data to compare. The excessive chip area required for these scan registers and the limited functional and performance tests provided by a single clock cycle operation are the two major drawbacks of LSSD design.

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Multiple-Cycle Level Sensitive SCAN Design

The present design reduces the overhead in the traditional Level Sensitive Scan Design (LSSD) by allowing a multiple cycle test operation between scan-in and scan-out operations. One extra pin and one AND gate are additionally provided to support the multiple cycle test operation. The traditional LSSD requires that all flip-flops and latches in one circuit macro be converted to scan registers. These registers are chained together and shift controlled by primary inputs and outputs. Tests are done by scanning (shifting) a set of test vectors into all registers, running one system clock cycle and scanning out all register data to compare. The excessive chip area required for these scan registers and the limited functional and performance tests provided by a single clock cycle operation are the two major drawbacks of LSSD design. The Multiple-Cycle Level Sensitive Scan Design (MLSSD) described here can reduce the number of latches converted to scan registers, perform a multiple system clock operation between scan-in and scan-out, and exercise a complete critical timing path by one test vector. The drawing shows the MLSSD structure with one additional pin "SCAN HOLD" and one additional AND gate over the traditional LSSD. The SCAN HOLD pin is kept high during scan operation. It turns low to block system data from a previous logic macro and can hold the scan register data as many clock cycles as needed. Test pattern generation...