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Synchronizing Graphics Data Streams to Alphanumeric Data Streams in Display Products

IP.com Disclosure Number: IPCOM000061828D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

DiNicola, PD: AUTHOR [+3]

Abstract

This article describes, in a controller-display terminal system, a subsystem for synchronizing graphics and alphanumeric (A/N) data output from respective data buffers to the cathode ray tube (CRT) display, and for interleaving that data transfer with other operations such as read/write between the refresh memories which store that data and the controller. In particular, the subsystem includes means for providing an enhanced I/O data refresh of the buffered graphics data during retrace of the CRT display beam. Fig. 1 shows a general block diagram of a graphics-A/N display system embodying the invention. The data bus 10 provides eight-bit bytes to an A/N Text Buffer 12 where they are stored as character points corresponding to the character display positions on the screen.

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Synchronizing Graphics Data Streams to Alphanumeric Data Streams in Display Products

This article describes, in a controller-display terminal system, a subsystem for synchronizing graphics and alphanumeric (A/N) data output from respective data buffers to the cathode ray tube (CRT) display, and for interleaving that data transfer with other operations such as read/write between the refresh memories which store that data and the controller. In particular, the subsystem includes means for providing an enhanced I/O data refresh of the buffered graphics data during retrace of the CRT display beam. Fig. 1 shows a general block diagram of a graphics-A/N display system embodying the invention. The data bus 10 provides eight-bit bytes to an A/N Text Buffer 12 where they are stored as character points corresponding to the character display positions on the screen. The stored bytes of data are read out in raster scan fashion and provided to an A/N Lookup Table 14 where the pel (picture element) data corresponding to the actual display is read out. This pel data is provided in nine-bit-wide character slices to a Select circuit 16 which, when the A/N mode is selected, provides the pel data to CRT 18. Data bus 10 also provides eight-bit byte data to a Graphics Pel Buffer 20. The pel data provided on data bus 10 is stored as raw pel data, and is read out in raster scan fashion in eight-bit bytes to Select circuit 16. When Select circuit 16 selects the graphics mode, this pel data is provided to CRT 18. Initialization and other data is also provided on data bus 10 to a CRT Controller 22, which stores that data and uses it to set up the synchronized timing circuitry to provide the pulse waveforms necessary to control CRT 18 and Buffers 12 and
20. In conjunction with the provision of the appropriate pulse waveforms for Graphics Pel Buffer 20, a Ring Counter 24 is also employed. Fig. 2 is a more detailed diagram of the Ring Counter 24. It includes a Ring Counter Chip 26 and a NAND gate 28 having inverting inputs. The Ring Counter Chip 26 generates the graphics word clock, a square-wave pulse waveform synchronized with, and exactly 1/16, the frequency of the Dot Clock Oscillator (not shown). The Ring Counter Chip 26 also produces seven other clock signals identical to the word clock but phase lagged one to the next by one dot clock cycle. These other clock signals are necessary for the various operations involved in the I/O and read out operations of the buffer. The Dot Clock Oscillator provides square waves at the pel rate, and is used for reference by the entire CRT control system. As shown, the Dot Clock Oscillator output is provided to the clock input of Ring Counter Chip 26. The Load Control signal and Blanking signal are provided to the inputs of NAND gate 28. With the Blanking signal active, the Load Control signal operates to reset the Ring Counter 24, in a manner described below. With the Blanking signal inactive, i.e., during normal video,...