Browse Prior Art Database

Data Rate Matching Buffer

IP.com Disclosure Number: IPCOM000061829D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Beauvais, KA: AUTHOR

Abstract

A system allows simultaneous writing and reading, at different data rates of a device channel adapter buffer when using the data streaming Protocol on the 370 I/O Printer Interface. Fig. 1 is a diagram of the principle components used to control the writing and reading of the device channel adapter buffer during data transfer with the system channel. During data transfer, data from the system channel will be written into the device channel adapter buffer as it is received (demand write cycle) at a higher rate than the data read from it that is to be transferred to the device common buffer (allow read cycle). The logic controls for the device common buffer will grant priority to allow data transfers between the device channel adapter buffer and the device common buffer.

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Data Rate Matching Buffer

A system allows simultaneous writing and reading, at different data rates of a device channel adapter buffer when using the data streaming Protocol on the 370 I/O Printer Interface. Fig. 1 is a diagram of the principle components used to control the writing and reading of the device channel adapter buffer during data transfer with the system channel. During data transfer, data from the system channel will be written into the device channel adapter buffer as it is received (demand write cycle) at a higher rate than the data read from it that is to be transferred to the device common buffer (allow read cycle). The logic controls for the device common buffer will grant priority to allow data transfers between the device channel adapter buffer and the device common buffer. The principle components of the device data flow relating to this disclosure are illustrated in Fig. 1. Data is written into the device channel adapter buffer upon receipt from the ssystem channel. If a read cycle is in process, the write controls block the transfer to the device common buffer and force a write cycle. When the write cycle is complete, the buffer returns to a continuous read cycle mode and transfers data to the device common buffer when the device common buffer logic controls allow priority. The system channel request counter is initially set by the device logic to a byte count equal to the number of bytes that are expected to be transferred for the received command. This counter is decremented for each data byte requested from the system channel. The contents of this counter are compared to 0's to determine when the last system request, for a byte of data to be transferred, has been requested. The system channel response counter is initially set by the device logic to a byte count equal to the number of bytes that are expected to be transferred for the received command. This counter is decremented for each data byte received from the system channel. The contents of this counter are compared to the contents of the system channel request counter to determine when the last byte to be transferred has been received. If the last system request compare is active, then the system data transfer is complete. If the last system request compare is not active, then system data transfer has been temporarily suspended. The value in this counter is used to address the device channel adapter buffer on write cycles. The common buffer request counter is initially set by the device logic to a byte count equal to the number of bytes that are expected to be transferred for the received command. This counter is decremented for each request allowed by the device common buffer controls to transfer data. The contents of this counter are compared to the contents of the system channel resp...