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Fast Implementation of Group Carry Look-Ahead in a CMOS Adder

IP.com Disclosure Number: IPCOM000061835D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Curran, BW: AUTHOR [+2]

Abstract

A method is described by which group carries in a binary adder can be generated with less delay than previously, when implemented in technologies that do not allow dot ORing, such as CMOS. A new set of equations is provided for CMOS, which supports the regular AND-OR and OR- AND structures used to obtain the group transmit and forward generate terms defined in the new equations. One traditional way to add binary numbers is to divide the operands into groups (of usually four or eight bits each) and generate a sum and an incremented sum for each group. The incremented sum represents the case of the sum assuming a carry into the group. Once the actual carry into each group can be determined, it is used to select either the sum or the incremented sum. The final output of the adder becomes the sum selected for each group.

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Fast Implementation of Group Carry Look-Ahead in a CMOS Adder

A method is described by which group carries in a binary adder can be generated with less delay than previously, when implemented in technologies that do not allow dot ORing, such as CMOS. A new set of equations is provided for CMOS, which supports the regular AND-OR and OR- AND structures used to obtain the group transmit and forward generate terms defined in the new equations. One traditional way to add binary numbers is to divide the operands into groups (of usually four or eight bits each) and generate a sum and an incremented sum for each group. The incremented sum represents the case of the sum assuming a carry into the group. Once the actual carry into each group can be determined, it is used to select either the sum or the incremented sum. The final output of the adder becomes the sum selected for each group. For sufficiently wide binary adders the critical delay path is through that portion of the logic that creates the group carries. A faster method of obtaining the group carries will thus result in a faster adder. The equations that are traditionally used to obtain the group carries in a 16-bit adder with input operands a0, ... a15 and b0, ... b15 (assuming four-bit groups) are as follows: Bit Propagate and Generate:

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The implementation of the above functions in CMOS requires two levels of logic. The following set of equations results in a faster adder when implemented in CMOS...