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Complementary FET Bipolar Circuit

IP.com Disclosure Number: IPCOM000061841D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Montegari, FA: AUTHOR

Abstract

This disclosure suggests the addition of a bipolar complementary emitter follower driver to a complementary metal oxide semiconductor (CMOS) logic circuit. The modification will improve its ability to drive highly capacitive loads and long metallurgy lines. The field-effect transistor bipolar circuit (FETBI), as shown in the drawing, combines complementary FET inverters and complementary bipolar emitter followers. This produces a circuit which has the low power dissipation of CMOS along with the ability to drive highly capacitive loads which bipolar logic circuits have. Fundamental to the circuit is transistor T2 connected between the drain terminals of T1 and T3, the latter normally connected together in an FET inverter. The device provides a voltage translation between the bases of bipolar emitter followers T4 and T5.

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Complementary FET Bipolar Circuit

This disclosure suggests the addition of a bipolar complementary emitter follower driver to a complementary metal oxide semiconductor (CMOS) logic circuit. The modification will improve its ability to drive highly capacitive loads and long metallurgy lines. The field-effect transistor bipolar circuit (FETBI), as shown in the drawing, combines complementary FET inverters and complementary bipolar emitter followers. This produces a circuit which has the low power dissipation of CMOS along with the ability to drive highly capacitive loads which bipolar logic circuits have. Fundamental to the circuit is transistor T2 connected between the drain terminals of T1 and T3, the latter normally connected together in an FET inverter. The device provides a voltage translation between the bases of bipolar emitter followers T4 and T5. This voltage translation provided by T2 eliminates a performance degrading "dead zone" which would otherwise occur if the bipolar bases were directly connected to each other. The dead zone would be VbeT4 + VbeT5 and result from one bipolar device turning off well before the other turns on. The problem indicated above is avoided by PFET T2. Its source is connected to the drain of T1 and base of T4, with both its gate and drain connected to the drain of T3 and base of T5. This causes T2 to function as a P type source follower with a total source - drain voltage drop of ~1 V. This bias placed between the bases of T4...