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Reconfigurable Single/Dual Port RAM System

IP.com Disclosure Number: IPCOM000061853D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Schoenike, RL: AUTHOR

Abstract

A system, which includes two RAM circuits on a single chip for internal register storage, can be configured as a single port configuration or as a dual port configuration memory system. In the dual port configuration, the RAM circuits operate as a single memory system and allow two words to be read simultaneously from the memory system. In a single port configuration the RAM circuits can be addressed independently which facilitates the enlargement of data storage. Referring to the figure, a memory system 10 includes a micro-instruction register 12 and a decode circuit 14. A central processing unit determines which mode memory system 16 should be configured and then generates the proper micro-instruction. The micro-instructions are fed to register 12 and decoded by circuit 14.

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Reconfigurable Single/Dual Port RAM System

A system, which includes two RAM circuits on a single chip for internal register storage, can be configured as a single port configuration or as a dual port configuration memory system. In the dual port configuration, the RAM circuits operate as a single memory system and allow two words to be read simultaneously from the memory system. In a single port configuration the RAM circuits can be addressed independently which facilitates the enlargement of data storage. Referring to the figure, a memory system 10 includes a micro-instruction register 12 and a decode circuit 14. A central processing unit determines which mode memory system 16 should be configured and then generates the proper micro-instruction. The micro-instructions are fed to register 12 and decoded by circuit 14. Circuit 14 decodes the micro-instructions and feeds a signal to either latch 18 or latch 20. The system 10 normally operates in the dual port mode. Thus, latch 18 is activated only when the single port mode of operation is desired. Moreover, if the single port mode is selected, latch 20 is also activated in order to facilitate the selection of RAM circuit 22 or RAM circuit 24. The system 10 also includes a write/enable logic circuit 26 which senses the outputs of latches 18 and 20 and generates and transmits an appropriate write/enable signal to RAM circuit 22 and/or RAM circuit 24. Address registers 28 and 30, which are coupled to RAM circuits 22 a...