Browse Prior Art Database

Submicrometer Mosfets

IP.com Disclosure Number: IPCOM000061855D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Barber, J: AUTHOR [+4]

Abstract

An FET having features smaller than conventional photolithography permits can be fabricated by the following process. Referring to Fig. 1, a silicon wafer 10 has a gate silicon oxide layer 12, a polysilicon layer 14 and another silicon oxide layer 16 applied sequentially. A thick layer of photoresist is subsequently applied over silicon oxide layer 16 and exposed using conventional processes. The exposure and development parameters of the resist are chosen such that undercuts having width D are created. The base width W1 of the resist pedestal 18 is less than the width W2 at the top of the resist pedestal 18. Using wet or dry etch techniques, oxide layer 16 is etched using the resist pedestal 18 as a mask. Upon stripping the resist pedestal, a silicon oxide pad 20 having width W1 remains, as seen in Fig 2.

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Submicrometer Mosfets

An FET having features smaller than conventional photolithography permits can be fabricated by the following process. Referring to Fig. 1, a silicon wafer 10 has a gate silicon oxide layer 12, a polysilicon layer 14 and another silicon oxide layer 16 applied sequentially. A thick layer of photoresist is subsequently applied over silicon oxide layer 16 and exposed using conventional processes. The exposure and development parameters of the resist are chosen such that undercuts having width D are created. The base width W1 of the resist pedestal 18 is less than the width W2 at the top of the resist pedestal 18. Using wet or dry etch techniques, oxide layer 16 is etched using the resist pedestal 18 as a mask. Upon stripping the resist pedestal, a silicon oxide pad 20 having width W1 remains, as seen in Fig 2. The polysilicon layer 14 is next etched using the silicon oxide pad 20 as a mask. The result is a narrow polysilicon line 22, as seen in Fig 3. With this concept, device features can be made smaller than the state-of-the-art photolithography allows.

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