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Input Circuit With Improved Negative Transient Noise Immunity

IP.com Disclosure Number: IPCOM000061863D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+2]

Abstract

Improved protection of address input circuits from negative voltage noise, e.g. the noise encountered during the high to low transition of a memory card address net, is achieved by the addition of a single transistor to the input circuit.

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Input Circuit With Improved Negative Transient Noise Immunity

Improved protection of address input circuits from negative voltage noise, e.g. the noise encountered during the high to low transition of a memory card address net, is achieved by the addition of a single transistor to the input circuit.

Referring to the figure, a negative undershoot in a signal to the pad results in T1 turning on when restore R is at ground potential, thus compromising any previously held latch data. The added transistor T2 provides latched data protection by forcing the input at node n to the latch 4 to a high level once a "true" signal is sent to push-pull driver 6. The gate of T2 connects to the gate of the "true" pullup device in driver 6. T2 is always activated within the address hold time.

The input latch will maintain a true state even when the pad has been at -2.0 volts for 20 nanoseconds.

Disclosed anonymously.

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