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Pinned Substrate for Circuit Chip Mounting

IP.com Disclosure Number: IPCOM000061871D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Bartlett, DA: AUTHOR [+3]

Abstract

The provision of recesses at the location of the heads of pins and respective lands in pinned substrates avoids possible interference with subsequently mounted circuit ch

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Pinned Substrate for Circuit Chip Mounting

The provision of recesses at the location of the heads of pins and respective lands in pinned substrates avoids possible interference with subsequently mounted circuit ch

Referring to the figure, substrate 1, such as ceramic, is formed with a recess 2 and metallized land 3 at each pin opening. Land 3 connects with circuit line 4 leading to chip connection pad 5. A pin 6 is inserted, swaged and soldered to the land. The land can be copper plated in the vicinity of the pin head with the remaining circuit line 4 chrome plated as a solder stop. Substrate 1 is formed with curved interfaces 7, 8 between the lines 4 and the lands 3 and pads 5, respectively. This enhances processing during substrate manufacturing, e.g. metalization integrity. The recessed pin prevents possible interference with the edge of a chip that may extend to the pin location. The head of pin 6 is solder bonded, e.g. PbSn bond 9, to land 3.

Disclosed anonymously.

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