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Common Tester for Multiple Array Chip Configuration

IP.com Disclosure Number: IPCOM000061892D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Cheng, FM: AUTHOR [+2]

Abstract

Failures in a memory using any array chip geometry can be found without changing the testing hardware in the storage control element (SCE) for the memory if the address register (Hamtsar) used by the hardware is controlled by a separate mask register (HAMR) of the same size as the address register.

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Common Tester for Multiple Array Chip Configuration

Failures in a memory using any array chip geometry can be found without changing the testing hardware in the storage control element (SCE) for the memory if the address register (Hamtsar) used by the hardware is controlled by a separate mask register (HAMR) of the same size as the address register.

The address in Hamtsar is advanced in a non-sequential manner by using the HAMR to control the bit ranges of the address to be stepped. A normal Hamtsar increment (decrement) will only operate on those bits of the Hamtsar which do not have a corresponding one bit in the HAMR. The HAMR bits are selected so chips are tested one at a time when the Hamtsar is incremented through its address range. When these normally updateable bits of the Hamtsar reach a value of all ones, the masked address bit field in Hamtsar is incremented by one, the bit error counters are reset and the Hamtsar is incremented through the array address range.

This hardware allows the tester to exercise the memory in a manner which enables it to locate any failing array chips without that hardware being dependent on the array chip address geometry. Thus, error counts can be obtained on a per chip basis. This is useful in implementing a spare array chip substitution algorithm.

Disclosed anonymously.

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