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Improved Scheduling in a Logic Simulator

IP.com Disclosure Number: IPCOM000061917D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Buonomo, JM: AUTHOR [+2]

Abstract

There are two general types of logic simulators, event driven simulators and compiled model simulators. In event driven simulators, if a gate changes, all the gates it feeds are added to the bottom of the list of gates that need be evaluated. In a compiler model simulator, signals are ordered so that in one pass all gates are evaluated.

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Improved Scheduling in a Logic Simulator

There are two general types of logic simulators, event driven simulators and compiled model simulators. In event driven simulators, if a gate changes, all the gates it feeds are added to the bottom of the list of gates that need be evaluated. In a compiler model simulator, signals are ordered so that in one pass all gates are evaluated.

It has been found that improved performance in an event driven simulator can be obtained by giving each gate an order or rank number as is done in a compiled simulator. The entries in the list of gates to be evaluated are then ordered in accordance with this number.

This algorithm will guarantee that a given block will have all of its inputs evaluated when the block gets called from the time queue. The second step is to use these level numbers to sort the queue before the blocks are called by the simulator. During the sorting process, blocks that appear a multiple number of times will be removed from the queue since a single call will be sufficient.

In a normal simulation environment where each of the blocks can have a multiple number of inputs, this process can save many simulation event calls and, therefore, increase the simulator performance with the smaller cost of sorting and reducing the time queues.

Anonymous.

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