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Browse Prior Art Database

Virtual Interrupt Mechanism

IP.com Disclosure Number: IPCOM000062025D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 4 page(s) / 56K

Publishing Venue

IBM

Related People

Goldstein, BC: AUTHOR [+3]

Abstract

The mechanism set forth provides the ability to define a mapping of arbitrary (software and hardware) interrupts into action routines for each distinct program environment. A queued hardware interface is used, thus avoiding the need to DISABLE interrupts. Also, the need for first level interrupt handlers (FLIHs) and second level interrupt handlers (SLIHs) is avoided. This implies higher performance and better CACHE hit ratios. Equally important, this mechanism is used as a means for inter-processor communication, where the requester is not aware of whether the receiver is on the same processor or a different one. Thus, the requester does not have to code alternative logic in its mainline paths depending upon whether a call is to be made on the same processor or on a different one.

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Virtual Interrupt Mechanism

The mechanism set forth provides the ability to define a mapping of arbitrary (software and hardware) interrupts into action routines for each distinct program environment. A queued hardware interface is used, thus avoiding the need to DISABLE interrupts. Also, the need for first level interrupt handlers (FLIHs) and second level interrupt handlers (SLIHs) is avoided. This implies higher performance and better CACHE hit ratios. Equally important, this mechanism is used as a means for inter-processor communication, where the requester is not aware of whether the receiver is on the same processor or a different one. Thus, the requester does not have to code alternative logic in its mainline paths depending upon whether a call is to be made on the same processor or on a different one. The problem of supporting processor communication (whether synchronous or interrupt driven) increases as we increase the number of possible interrupts; i.e., as we move to more and more asynchronous processing of major functions of VS systems (such as MVS IOS, the Auxiliary Storage Manager, Data Base Machines, Supervisor Machines, Lock Managers, etc.) newer types of interrupts will be defined, where interrupt now means "return information for an activity that was performed asynchronously". Given the existing interrupt structure, this will result in greater complexity in attempting to fit these new interrupts into the 5 existing classes supported by IBM System/370 and performance degradation in adding logic to these interrupt handlers to process the interrupts. Furthermore, with the possibility that a given function can either be performed on the same processor or on an asynchronous processor, the need exists for the requester of the function to be transparent to the physical location of the function rather than suffer the performance degradation (and possible migration inhibitors) in invoking the function. Similarly a function request need not always result in generating an interrupt. In some instances having the request merely queued would enable a software polling function to sort these requests for greater performance. This invention provides us with a mechanism for defining to the hardware an arbitrary number of interrupt handlers (therefore labeled as virtual) and a queued interface that avoids requiring interrupt handlers to DISABLE. The following new additions are made to the IBM System/370 architecture. 1. New instructions to define new interrupts (called service requests), and to either invoke, queue, receive, or purge service requests. 2. An INDIRECTION ARRAY (IA) maintained by the hardware, and is used by the hardware to access software-built structures. Theses additions are used in the following manner: The following hardware/software structures are required:

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where: the first five entries in the IA are reserved for the: Program Check, I/O, SVC, Machine Check, and External Interrupt Handlers. N speci...