Browse Prior Art Database

Selection Scheme for MTL Cells With Split Emitters

IP.com Disclosure Number: IPCOM000062036D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

This article is directed to a means for enhancing the performance (by reducing the cycle time) of existing MTL (merged transistor logic) selection schemes by partitioning the Word Lines and Bit Lines in such a manner as to remove the need for a discharge/restore process in the selection cycle. The object of the disclosed selection scheme is to isolate the Source Line of a group of bits so that the diffusion capacitances of the unselected cell injectors do not interfere with the Source Line (SL) selection. This is possible only after the cell circuits are rearranged. As shown, cell injectors are connected to a common Source Line, and the split bottom emitters of the inversely operated transistors are tied to the left and right Bit Lines (BLs and BRs).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Selection Scheme for MTL Cells With Split Emitters

This article is directed to a means for enhancing the performance (by reducing the cycle time) of existing MTL (merged transistor logic) selection schemes by partitioning the Word Lines and Bit Lines in such a manner as to remove the need for a discharge/restore process in the selection cycle. The object of the disclosed selection scheme is to isolate the Source Line of a group of bits so that the diffusion capacitances of the unselected cell injectors do not interfere with the Source Line (SL) selection. This is possible only after the cell circuits are rearranged. As shown, cell injectors are connected to a common Source Line, and the split bottom emitters of the inversely operated transistors are tied to the left and right Bit Lines (BLs and BRs). A bit group is selected when SL is raised and the unselected bit group lines are lowered. Sensing signal is from the difference of IR drops on the two bit lines. References "Three-Dimensional Organization of I2L Memory Cells," IBM Technical Disclosure Bulletin 28, 3360- 3361 (January 1986); Siegfried K. Wiedmann, Denny D. Tang and Roderic Beresford, "High-Speed Split-Emitter I2L/MTL Memory Cell," IEEE J . of Solid- State Circuits, SC-16, 429-434 (October 1981).

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]