Browse Prior Art Database

Data Processing Verification

IP.com Disclosure Number: IPCOM000062047D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Beauvais, KA: AUTHOR [+3]

Abstract

A method is described for checking that all the data transferred for a given command, from a system channel to a device that buffers the data at different stages for logic manipulation, is processed correctly. This is accomplished by compare logic designed to check that the number of data bytes transferred from the system channel to the device channel adapter was consequently transferred to the device common buffer area. The principle components of the device data flow relating to this disclosure are illustrated in the figure. The data is written into the device channel adapter buffer upon receipt from the system channel and transferred to the device common buffer when read priority is given.

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Data Processing Verification

A method is described for checking that all the data transferred for a given command, from a system channel to a device that buffers the data at different stages for logic manipulation, is processed correctly. This is accomplished by compare logic designed to check that the number of data bytes transferred from the system channel to the device channel adapter was consequently transferred to the device common buffer area. The principle components of the device data flow relating to this disclosure are illustrated in the figure. The data is written into the device channel adapter buffer upon receipt from the system channel and transferred to the device common buffer when read priority is given. The residual byte counter is initially set by the device logic to a byte count equal to the number of bytes that are expected to be transferred for the received command. This counter is decremented for each 370 interface data response tag received from the system channel. The device common buffer contains two buffer areas used in a ping/pong operation. The data received from the device channel adapter buffer is stored in one of the two buffers while the other is available for down line processors (such as a character generator in the IBM 3800 Model 3 printer). This allows simultaneous operations. The device common buffer address register value is set by the device logic to point at the beginning location of the available buffer for the device channel adapter data transfer. The address is incremented for each device channel adapter request to store data to point to the next available location within the buffer. The down line processor (such as a character generator in the system printer) will fetch dat...