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Synchronous-To-Asynchronous Conversion Buffer and Application

IP.com Disclosure Number: IPCOM000062064D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Kim, MY: AUTHOR [+2]

Abstract

In large, tightly coupled multiprocessor systems, typically a very large amount of main memory is shared. This amount can be many megabytes. Whenever there is an imminent system failure, it is necessary to save this shared memory and restore it later. However, the amount of time available is crucial and the amount to be saved is large. Any attempt to save this by serial storage on a single disk is too time consuming. It would be desirable to be able to store the information on disks accessed in parallel. However, each disk must work asynchronously with respect to the others while memory words are read synchronously. This presents a serious difficulty in maintaining logical consistency as well as in timing (clocking) such an operation. A desirable type of function is shown schematically in Fig. 1.

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Synchronous-To-Asynchronous Conversion Buffer and Application

In large, tightly coupled multiprocessor systems, typically a very large amount of main memory is shared. This amount can be many megabytes. Whenever there is an imminent system failure, it is necessary to save this shared memory and restore it later. However, the amount of time available is crucial and the amount to be saved is large. Any attempt to save this by serial storage on a single disk is too time consuming. It would be desirable to be able to store the information on disks accessed in parallel. However, each disk must work asynchronously with respect to the others while memory words are read synchronously. This presents a serious difficulty in maintaining logical consistency as well as in timing (clocking) such an operation. A desirable type of function is shown schematically in Fig. 1. Words of normal memory word length, B, (32, 64 bits or larger) are read one word at a time and placed into the rows of a Conversion Buffer as shown. After some number of such words are entered, it is desired to serially shift out the columns of the Conversion Buffer, each column going to a separate disk. The memory words are thus scattered across b disks, each disk containing one bit of each word as in Fig. 1 (a), or across z disk pack cylinders as in Fig. 1
(b). The bits of sequential words must be stored sequentially along the tracks (records) of each disk, and each word must correspond logically to the same bit position within the record as shown. However, writing the columns to the disks cannot be done synchronously since it is not possible to synchronize the spinning of multiple disks to the required accuracy. Hence, the columns should be read (and later written back) independently, with separate clocks as shown, if necessary. This creates some serious buffering and clocking problems if ordinary RAM (random-access memory) is used for the Conversion Buffer. The 2-ported, functional display RAM chips of [1] provide a very simple and versatile way of achieving a synchronous-to-asynchronous, parallel read-out. The basic structure of this RAM is shown in Figs. 2 and 3. It consists of essentially two ports: 1) the usually dynamic type memory chip with its primary I/O port, and 2) a secondary port and row buffer which, once loaded from the main array, is completely independent and asynchronous from the primary port. One simple version of this chip is shown in Fig. 2 where the secondary I/O is obtained from serial shifting of the slave portion of the row buffer. Any access through the primary port with a Row Address will latch N sense amplifier/latches (typically N=256). If the Load Master Register (LMR) signal is on, the Isolator switches will be on and load the 256 sense amplifier/latches into the Master portion of the row buffer. LMR is then made invalid and isolates the row buffer from the storage array. The storage array can be accessed through the primary port, asynchronousl...