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Self-Test N-Stream Online Isolation

IP.com Disclosure Number: IPCOM000062071D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 4 page(s) / 50K

Publishing Venue

IBM

Related People

Smith, GL: AUTHOR

Abstract

Utilizing an n-stream simulation program, which can have performance as much as n times as fast as a conventional simulator provides a practical process for identifying the first failing self-test pattern even in the presence of large circuit counts, large pattern counts, and arrays in the hardware under test. It is the speed of the n-stream simulator which makes the processor practical for large logical entities. Means must be provided for extracting the value of all latches and arrays in the hardware under test. Typically, scan paths are used for this purpose. Also, means must exist for loading latches with reproducible pseudo-random patterns and for compressing latch values into accessible signature registers.

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Self-Test N-Stream Online Isolation

Utilizing an n-stream simulation program, which can have performance as much as n times as fast as a conventional simulator provides a practical process for identifying the first failing self-test pattern even in the presence of large circuit counts, large pattern counts, and arrays in the hardware under test. It is the speed of the n-stream simulator which makes the processor practical for large logical entities. Means must be provided for extracting the value of all latches and arrays in the hardware under test. Typically, scan paths are used for this purpose. Also, means must exist for loading latches with reproducible pseudo- random patterns and for compressing latch values into accessible signature registers.

Means must also exist for loading reproducible patterns into arrays and for compressing array values into accessible signature registers.

The patterns loaded into the arrays should be pseudo-random because coverage is improved and test lengths can be shortened. The hardware under test is connected to a computer capable of running an n-stream hardware simulation of the hardware under test, where n is greater than one. The connection is such that the values of latches and arrays extracted from the hardware can be loaded into the simulation model. An n-stream simulator differs from a conventional simulator in that n different states of the machine are simulated in parallel. In many computer architectures, an n-stream simulator can run much faster than a conventional single-stream simulator because machine instructions are available for execution of Boolean functions on n bits. In general, an n-stream simulator keeps n copies of all latches and arrays. Because the amount of space required for large arrays may be prohibitive, large arrays are stored on an incremental basis. A single copy of each array word is maintained for all of the n streams except for words with different values in different streams. In such a case, the address is flagged and a sufficient number of copies of the word are kept to allow the simulator to access the proper value of the word for all n streams. The operation of the invention is such that most addresses only require a single copy and the space requirement is greatly reduced. Similarly, the connection between the tester and the computer need only transmit sufficient information to initialize these values. Therefore, the traffic on the connection can be a great deal less than that required to transmit n full copies of the arrays. A file of good machine signatures is provided. A self-test consists of one or more tests. Each test starts off with initialization of the pseudo-random generator(s) with a unique (to that test) seed, the initialization of the arrays with unique (to that test) pseudo-random patterns, and the initialization of the signature register(s). A given number of patterns are then issued, where one pattern consists of loading the latches from the...