Browse Prior Art Database

# Decimal Parity Prediction

IP.com Disclosure Number: IPCOM000062079D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 52K

IBM

## Related People

Curran, BW: AUTHOR

## Abstract

OVERVIEW A method to predict the parity of a decimal sum or difference is described. It differs from other prediction schemes in that only two parities are predicted for each digit position. The additional circuitry to implement this prediction is not excessive. It can easily be designed to also predict the parity of a binary addition. BACKGROUND Single-bit errors in an adder can be detected by comparing the predicted parity of an addition/subtraction with the actual parity of that operation. All single faults within a circuit are detectable if each single fault creates (at most) a one-bit error in the result. To reduce the delay through a multi-byte decimal (or binary) adder, two sums are calculated for each digit (or byte) position.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

Decimal Parity Prediction

OVERVIEW A method to predict the parity of a decimal sum or difference is described. It differs from other prediction schemes in that only two parities are predicted for each digit position. The additional circuitry to implement this prediction is not excessive. It can easily be designed to also predict the parity of a binary addition. BACKGROUND Single-bit errors in an adder can be detected by comparing the predicted parity of an addition/subtraction with the actual parity of that operation. All single faults within a circuit are detectable if each single fault creates (at most) a one-bit error in the result. To reduce the delay through a multi-byte decimal (or binary) adder, two sums are calculated for each digit (or byte) position. They correspond to a) the sum if the carry into that digit position is zero and b) the sum if the carry into that digit position is a one. The carry bit from the carry look-ahead logic then selects the correct sum. Similarly, the parity of these two sums can be predicted, and the carry bit can be used to select the correct predicted parity. THEORY Consider the addition or nines-complement subtraction of two BCD digits A and B,

(Image Omitted)

where B' is the nines complement of B. Now, since not all sums are valid BCD digits, an excess-six correction may be required (when result of addition > 9). Two results can be obtained: one assumes that the carry into the digit position is zero and the other that the carry into the digit position is one,

(Image Omitted)

Parity can be predicted for each of these operations, nines-complementing, addition, excess-six correction and incrementing. The function of the nines- complement logic is described by the following Boolean equations,

(Image Omitted)

To simplify the prediction of the parity of B', we include the terms b8 b4 and b8 b2 in b8'. This wil...