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Accordion Start-Stop Sequencer for a Variable Cycle Storage Controller

IP.com Disclosure Number: IPCOM000062091D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Malmquist, CA: AUTHOR [+2]

Abstract

A memory implementation that offers variable-length data transfers requires its control signals to be active a length of time that corresponds to data transfer length. If only one sequencer is used in this situation, the decoding of states to turn the control signals on and off is different for each type of transfer, e.g., 4-byte, 8-byte, 16-byte, 24-byte or 32-byte. If two sequencers are used, the decoding needed to turn the controls on and off is the same for each transfer length. The benefits of this implementation are less decoding, less hardware and ease of change if the timing of memory interface changes. The two-sequencer implementation works as follows. As seen in the block diagram, when a memory bus grant 1 is given, the start sequencer 2 instructs the memory controls 3 to turn on in a fixed sequence.

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Accordion Start-Stop Sequencer for a Variable Cycle Storage Controller

A memory implementation that offers variable-length data transfers requires its control signals to be active a length of time that corresponds to data transfer length. If only one sequencer is used in this situation, the decoding of states to turn the control signals on and off is different for each type of transfer, e.g., 4- byte, 8-byte, 16-byte, 24-byte or 32-byte. If two sequencers are used, the decoding needed to turn the controls on and off is the same for each transfer length. The benefits of this implementation are less decoding, less hardware and ease of change if the timing of memory interface changes. The two-sequencer implementation works as follows. As seen in the block diagram, when a memory bus grant 1 is given, the start sequencer 2 instructs the memory controls 3 to turn on in a fixed sequence. The precise order and timing of the signals depends on whether the signal is a fetch or a store. The memory command register 4 holds the instruction sent by the subunit requesting memory service and contains the length and fetch/ store information. This length decode 5 is loaded into the end sequencer 6 by an enable that is sent by the start sequencer 2. The end sequencer then starts to run and counts out the length of transfer and finally terminates the memory control signals in the proper order.

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