Browse Prior Art Database

Logic Interface to Allow High Performance Event Tracing With Low Performance Monitoring Devices

IP.com Disclosure Number: IPCOM000062092D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 4 page(s) / 46K

Publishing Venue

IBM

Related People

Ramer, SJ: AUTHOR [+2]

Abstract

This trace interface allows the monitoring or tracing of events that occur randomly in a high speed device by a lower speed device. The tools used to observe the behavior of the latest generation computer devices are often previous generation designs. The tools are often designed in a slower technology than that used by the device to be monitored. This design makes it possible to use the old, lower performance devices to monitor the new, faster devices by providing an interface to capture selected random events in the faster devices and to pass the resulting data to the lower speed device in a consistent manner without significant information loss.

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Logic Interface to Allow High Performance Event Tracing With Low Performance Monitoring Devices

This trace interface allows the monitoring or tracing of events that occur randomly in a high speed device by a lower speed device. The tools used to observe the behavior of the latest generation computer devices are often previous generation designs. The tools are often designed in a slower technology than that used by the device to be monitored. This design makes it possible to use the old, lower performance devices to monitor the new, faster devices by providing an interface to capture selected random events in the faster devices and to pass the resulting data to the lower speed device in a consistent manner without significant information loss. The trace interface of this design makes use of the relatively low average rate of the events being traced to capture and pass information to the trace device at the trace device interface rate. The trace interface detects the cases when the events being traced are occurring at a faster rate than can be accommodated by the trace device. In these cases, the trace interface selectively transfers a subset of the total set of events being traced to the trace device. Status information is also passed to the trace device that allows the information being traced to be displayed without error or loss of useful content. The trace interface described in the present design can be used to trace any type of randomly occurring event. The specific implementation described is used to trace instruction branches taken by a microprocessor. For each instruction branch taken, the trace interface attempts to pass to the trace device, the address of the source branch instruction, and the address of the instruction to which the branch is made. In the general case, the trace interface will be successful in passing both the source and target instruction addresses to the trace device. There are special cases when the microprocessor may execute successive branch instructions at a faster rate than the trace device can accept the trace information. These cases occur when several branch instructions are executed sequentially. In these cases the initial source branch instruction address is passed to the trace device and subsequently the target instruction addresses are passed to the trace device without the intervening source instruction addresses. In these cases, the target instruction addresses are the subsequent source instruction addresses, so no necessary trace information is lost when the source instruction addresses are omitted from the trace data. Each address passed to the trace device by the trace interface includes a status bit that identifies the address as either a source or target address. This status information allows the trace device to display the trace information without error even when some of the source instruction addresses have not been included in the trace data. The figure shows the logic circuitry...