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Automatic Pattern Generation for Self-Testing Displays

IP.com Disclosure Number: IPCOM000062093D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Evans, CN: AUTHOR [+2]

Abstract

In a CRT color display a pattern generator is activated when externally supplied horizontal sync pulses are absent and a test pattern is displayed. This provides self-test of a display at switch on and automatic self-testing in the event of system failure. The test pattern is a series of horizontal colored bars generated by a counter which is disabled by horizontal sync pulses. The attached circuit diagram shows a pattern generator for a color monitor. While the logic interface cable is connected, no pattern is generated, but when removed, a signal is generated which displays horizontal color bars on the screen. This enables diagnosis of horizontal scan, vertical scan and each of the three video amplifiers.

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Automatic Pattern Generation for Self-Testing Displays

In a CRT color display a pattern generator is activated when externally supplied horizontal sync pulses are absent and a test pattern is displayed. This provides self-test of a display at switch on and automatic self-testing in the event of system failure. The test pattern is a series of horizontal colored bars generated by a counter which is disabled by horizontal sync pulses. The attached circuit diagram shows a pattern generator for a color monitor. While the logic interface cable is connected, no pattern is generated, but when removed, a signal is generated which displays horizontal color bars on the screen. This enables diagnosis of horizontal scan, vertical scan and each of the three video amplifiers. Horizontal Sync Detect This portion of the circuit disables the generator when a horizontal sync signal is present from the logic. When the sync pulse is high, transistor Q1 is turned on and capacitor C1 is discharged. The duty cycle of horizontal sync is unimportant as the discharge time constant of C1 is much shorter than the charge time constant through R1. As C1 is discharged, Q2 is off and so the clear inputs to the counter are high and all outputs are low. If the horizontal sync signal is removed, Q1 is off, C1 is allowed to charge, Q2 is on and the counter is no longer disabled. Vertical Synchronization To ensure color bars are produced which are stable on the screen, the counter must be reset at every vertical retrace. This signal is taken from the vertical amplifier output as a 40 V pulse to provide the vertical retrace from bottom to top of the screen. When no logic vertical sync is present, the vertical amplifier will free-run. This signal is fed through D1, a 20 V zener diode, and clamped to +5 V through D2 to make it TTL (transistor-transistor logic) compatible and is fed to the clear inputs of the counter. This has the effect of resetting the counter during every vertical...