Browse Prior Art Database

Adjustable Reset Voltage for a Forward Converter

IP.com Disclosure Number: IPCOM000062094D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Kress, JE: AUTHOR [+2]

Abstract

This article describes a circuit arrangement which uses a buck-boost converter to discharge the reset capacitor of a forward converter into the bulk input voltage. In some existing forward converter such as shown in Figs. 1a and 1b, the use of 800 V transistors is required which permits a maximum duty cycle of 0.5. An unequal number of turns in the primary and reset windings will improve one at the expense of the other. If NR = NP, then the voltage that Q1 must withstand is VQ = 2VB. The maximum duty cycle is limited by the reset time of the transformer. (Image Omitted) For the standard forward converter, because VR = VP, the maximum allowed duty cycle is 0.5.

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Adjustable Reset Voltage for a Forward Converter

This article describes a circuit arrangement which uses a buck-boost converter to discharge the reset capacitor of a forward converter into the bulk input voltage. In some existing forward converter such as shown in Figs. 1a and 1b, the use of 800 V transistors is required which permits a maximum duty cycle of 0.5. An unequal number of turns in the primary and reset windings will improve one at the expense of the other. If NR = NP, then the voltage that Q1 must withstand is VQ = 2VB. The maximum duty cycle is limited by the reset time of the transformer.

(Image Omitted)

For the standard forward converter, because VR = VP, the maximum allowed duty cycle is 0.5. The circuit arrangement disclosed herein uses a buck-boost converter to discharge the reset capacitor of a forward converter into the bulk input voltage, as shown in Figs. 2a and 2b, using the equation, VP*D = VR*(I-D), derived previously,

(Image Omitted)

This is recognized as the inverse of the control of a buck-boost regulator, and because VB is constant, VR can be properly controlled if Q2 is off whenever Q1 is on and vice-versa. A slight deviation from this control algorithm may be needed to account for losses and non- ideal coupling of NR with NP. The size of L and C in the reset circuit are dictated by the allowable ripple in VR during the reset interval and the peak current experienced by Q2. The worst-case voltage that the transistors must withstand o...