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Personalizable RAM Design Using Word Line Movement

IP.com Disclosure Number: IPCOM000062104D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 77K

Publishing Venue

IBM

Related People

Dansky, AH: AUTHOR [+2]

Abstract

Personalizable random-access memory (RAM) devices used in state-of- the-art masterslices generally require in the order of four transistors per memory cell. This article concerns the design of a personalizable RAM in which only the two transistors already available in the full logic cell of an advanced design masterslice are required. The advanced design masterslice circuit shown in Fig. 1b uses a DTL (diode-transistor logic)-type circuit employing low barrier SBDs (Schottky barrier diodes) as the logic element. The memory cell uses two transistors for storage and employs four diodes for writing and reading through the bit lines. This is a difficult approach in comparison to the use of transistors, which have a base mode which can be lowered to shut off the transistor, as shown in Fig.

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Personalizable RAM Design Using Word Line Movement

Personalizable random-access memory (RAM) devices used in state-of- the-art masterslices generally require in the order of four transistors per memory cell. This article concerns the design of a personalizable RAM in which only the two transistors already available in the full logic cell of an advanced design masterslice are required. The advanced design masterslice circuit shown in Fig. 1b uses a DTL (diode-transistor logic)-type circuit employing low barrier SBDs (Schottky barrier diodes) as the logic element. The memory cell uses two transistors for storage and employs four diodes for writing and reading through the bit lines. This is a difficult approach in comparison to the use of transistors, which have a base mode which can be lowered to shut off the transistor, as shown in Fig. 1a, thereby isolating the unselected cells during a read or write operation. This difficulty is resolved by shifting the word lines of the selected row of cells up or down by a sufficient magnitude of voltage so that the unselected row of cells will be unaffected by the bit line voltage variations and therefore will be protected from a disturb condition. In the disclosed implementation (Fig. 2), the word lines are shifted up since the three diodes have their anodes connected to the memory cell. Alternatively, if the three diodes were reversed with their cathodes connected to the memory cell, the word lines would be shifted down for the row of selected cells, requiring high currents to flow into the cell on the zero side in order to write the cell. The first approach was chosen, the word lines being shifted up sufficiently to provide good noise margin and to avoid disturbs. The operations of stand-by (unselected) read and write are outlined with reference to the Fig. 2 circuit. Stand-by (Unselected) Operation In the stand-by operation, the two word lines are in the low state. A cross section of the array indicating the operating levels on the word and bit lines is shown in Fig. 2. The word lines are maintained in the low state by the input to the decoder being down
(.25 V); node D1 is up, node D2 is down (1.05 V), node D3, which is the upper word line (UWL), is in its low state, and the lower word line (LWL) is also in the low state. Since node D2 is at l.05 volts, and node D4 is clamped to 1.7 volts plus VFHB = 2.25 V, then TD2 is off and node D3 is held low by reason of TD3 (an emitter follower) being on. The LWL is held to 0.25 volt since node D1 is high and therefore TW1 is on. The write bit line left (WBLL) and write bit line right (WBLR) are both in the high state since the write control (WC) inputs are in the low state (STDBY). The read bit line (RBL) is low and therefore TR1 is off, node SA1 is at ground and node D0 is high (1.3 volts). The three memory cell low barrier Schottky diodes DW1, DW2 and DR1 are all reverse biased. Read Operation Referring again to Fig. 2, the control input to the...