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DMA Memory Controller

IP.com Disclosure Number: IPCOM000062109D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Stucka, SE: AUTHOR [+2]

Abstract

This article describes a DMA controller that supports two addressing modes. The first mode is synchronous addressing by two input channels and the second mode, asynchronous, indirect addressing by a processor. Included are four options for disabling the channel accesses when address boundaries are encountered. The first mode of addressing, i.e., synchronous two channel, is the default mode. When the processor addresses the memory in the second mode, it overrides the first mode. The first mode supplies access to the memory on alternate cycles for each input channel. The controller alternates between the two channels while in the first mode even though every cycle allocated to a channel need not be utilized.

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DMA Memory Controller

This article describes a DMA controller that supports two addressing modes. The first mode is synchronous addressing by two input channels and the second mode, asynchronous, indirect addressing by a processor. Included are four options for disabling the channel accesses when address boundaries are encountered. The first mode of addressing, i.e., synchronous two channel, is the default mode. When the processor addresses the memory in the second mode, it overrides the first mode. The first mode supplies access to the memory on alternate cycles for each input channel. The controller alternates between the two channels while in the first mode even though every cycle allocated to a channel need not be utilized. One channel cannot use the time cycle allocated to the other channel, however, even when the other channel is not utilizing it. The timing of signals controlling the first mode is shown in Fig. 1. The channel to which the memory is allocated is determined by RAMSEL(0) and RAMSEL(1). In the illustrated timing diagram, Channel #1 is selected when RAMSEL(0) is high and Channel #2, when RAMSEL(0) is low. The address (RAMADDR) is taken from Channel #1 during the period labelled #1 ADDR. (The XXX values designate times when the signals cannot be accepted as valid because of gate delays and the like.) The -RDREQ and -WRREQ signals are supplied by the channels and indicate that the channels are using their allocated memory cycles. The channels supply the signals at the same time as the memory address. These signals are shaped and synchronized to become the -OE and -WE signals used by the memory. The -OE and -WE signals are also supplied to the channel controllers to decrement the memory addresses. The DMA controller monitors the -OE and -WE signals to ascertain when a reserved cycle is being used. The presence of the signals causes the DMA controller to enable the address register in the controller corresponding to the channel in use and decrement it after the memory cycle. When the enabled address register value indicates that the final address is being approached, the signal -TERMCNT is activated. After the terminal count for a channel is reached, the channel is disabled. To extend the usefulness of the controller, e.g., in pipelined operations, the number of cycles before the terminal count that -TERMCNT is activated is selectable in the channel control bytes, as explained below in more detail. Access to the memory by the processor in the...