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Browse Prior Art Database

Power Supervisory Circuit

IP.com Disclosure Number: IPCOM000062119D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 89K

Publishing Venue

IBM

Related People

Carlsten, RW: AUTHOR

Abstract

This article describes a power supply supervisory circuit which enhances the attributes of commercially available voltage comparator integrated modules having an internal start latch circuit that prevents the generation of an erroneous undervoltage signal output at initial power on and further having an early power warning signal output for signaling in advance to a user that DC power is going to be shut off. The supervisory circuit utilizes the signal outputs of the IC module in combination with the functions of a Timer circuit, an OR gate, a Schmitt-triggered NAND circuit and a Delay circuit to control the shut-off of a DC power supply.

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Power Supervisory Circuit

This article describes a power supply supervisory circuit which enhances the attributes of commercially available voltage comparator integrated modules having an internal start latch circuit that prevents the generation of an erroneous undervoltage signal output at initial power on and further having an early power warning signal output for signaling in advance to a user that DC power is going to be shut off. The supervisory circuit utilizes the signal outputs of the IC module in combination with the functions of a Timer circuit, an OR gate, a Schmitt-triggered NAND circuit and a Delay circuit to control the shut-off of a DC power supply. The circuit's unique functions are best realized at initial power-up whereby the early power warning signal is used in conjunction with a Timer circuit to determine whether to shut down the power supply due to an undervoltage condition that normally would not be detected due to the start latch lock-out characteristic on the undervoltage output portion of the voltage comparator module. After initial power-up and a power-good condition exists, the power shut-down is accomplished using only the traditional overvoltage/undervoltage (OV/UV) outputs and not the early power warning output signal which operates independent of the supervisory circuits. Fig. 1 shows in block diagram form supervisory circuit 10, having common ground 24, interconnected to voltage comparator 11 through circuit output lines PWR GOOD 16 and PWR WARNING
17. Voltage comparator circuit 11 senses a plurality of voltages V1 through Vn and AC sense generally designated as 12 after being conditioned by resistor divider network 13. Voltage comparator 11 further has OV, UV and PWR WARNING outputs designated 11a, 11b and 11c, respectively. Outputs 11a and 11b are OR'ed through pull-up resistor 15 tied to a common reference voltage 14 to give a common PWR GOOD signal 16. Supervisory circuit 10 is comprised of OR gate 19, Timer 18, Delay 20 and a Schmitt-triggered NAND gate module 25 comprised of individual NAND gates 21, 22 and 23. The truth table shown in Fig. 2 describes the logic of the supervisory circuit at TURN ON, STEADY STATE, ABNORMAL SHUT DOWN and at NORMAL SHUT DOWN. At TURN ON, output 11c of module 11 is low, hence, input 19b of OR gate 19 is low, causing...