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Isolation and Interconnect Scheme for Sidewall Contact Structures

IP.com Disclosure Number: IPCOM000062124D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Monkowski, MD: AUTHOR

Abstract

Disclosed is a method of forming a buried oxide insulation under polysilicon in semiconductor devices. Previous processes used to form sidewall contact structures [1,2,3] have used either sidewall masked isolation (SWAMI) or epitaxial refill of a patterned oxide so as to provide a buried isolation layer. Both approaches lead to structures which are not defect-free. Also, the SWAMI process is complicated. In the present fill oxide isolation (FOXI) process, which is both simple and obtains a defect-free structure, a chemical vapor deposition (CVD) nitride layer 1 (Fig. 1) is deposited upon a thermally grown SiO2 layer 2. Layers 1 and 2 are patterned using reactive ion etch (RIE) and a photoresist mask with the pattern further etched using a directional silicon RIE to form a Si pedestal 3.

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Isolation and Interconnect Scheme for Sidewall Contact Structures

Disclosed is a method of forming a buried oxide insulation under polysilicon in semiconductor devices. Previous processes used to form sidewall contact structures [1,2,3] have used either sidewall masked isolation (SWAMI) or epitaxial refill of a patterned oxide so as to provide a buried isolation layer. Both approaches lead to structures which are not defect-free. Also, the SWAMI process is complicated. In the present fill oxide isolation (FOXI) process, which is both simple and obtains a defect-free structure, a chemical vapor deposition (CVD) nitride layer 1 (Fig. 1) is deposited upon a thermally grown SiO2 layer 2. Layers 1 and 2 are patterned using reactive ion etch (RIE) and a photoresist mask with the pattern further etched using a directional silicon RIE to form a Si pedestal
3. The entire structure is covered with a CVD SiO2 fill oxide layer 4 (Fig. 2) with its thickness being determined by the need for electrical isolation and sufficiently low capacitance. As an alternative, a thin thermal oxide may be grown prior to deposition in order to form a better interface. A CVD layer of polycrystalline silicon (fill poly) 6 (Fig. 3) (which may be doped or undoped), a layer of a silicide or a sandwich of the two is next deposited over the entire structure to a thickness equal to the step height 5 (Fig.
2). This fill poly requires low resistivity, the ability to be oxidized to form an insulating layer on top, and the ability to be planarized. The fill poly 6 (Fig. 4) is next planarized to the top of the fill oxide 4. The fill oxide provides a thick layer for endpoint detection and also encapsulates the active device area. This reduces contamination and damage which may result from planarization. Using a selective etch, the fill poly is recessed 6 (Fig. 5) to the level of or slightly beyond the top of the nitride 1.

A selective directional oxide RIE is next used to etch the fill oxide 4 (Fig. 6). This is etched to a level such that contact channels 7 are provided in which a sidewall contact may be formed. In this instance it may be desirable to termi...