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Dense Sense Amplifier/Latch Combination

IP.com Disclosure Number: IPCOM000062125D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Loehlein, WD: AUTHOR [+2]

Abstract

A modified sense amplifier is proposed that can act both as a sense amplifier and as a data-out latch. This effect is obtained by controlling the sense amplifier, using two signals which enable the merged sense amplifier/latch function. Fig. 1 is the diagram of a data path with a symbolically indicated memory cell for an array, as well as a flip-flop configuration T1 to T4 as a sense amplifier/latch combination. In the illustrated example, T1 and T2 designate an N-channel FET and T3 and T4 a P-channel FET complementary thereto. Other transistor combinations are, of course, equally conceivable. The word line and the bit lines (true and complement) are designated as WL, BLT and BLC. The further circuit elements will be referred to below.

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Dense Sense Amplifier/Latch Combination

A modified sense amplifier is proposed that can act both as a sense amplifier and as a data-out latch. This effect is obtained by controlling the sense amplifier, using two signals which enable the merged sense amplifier/latch function. Fig. 1 is the diagram of a data path with a symbolically indicated memory cell for an array, as well as a flip-flop configuration T1 to T4 as a sense amplifier/latch combination. In the illustrated example, T1 and T2 designate an N-channel FET and T3 and T4 a P-channel FET complementary thereto. Other transistor combinations are, of course, equally conceivable. The word line and the bit lines (true and complement) are designated as WL, BLT and BLC. The further circuit elements will be referred to below. A functional combination of a sense amplifier and a latch can be obtained by using a sense amplifier which can be isolated via T5, T6, T7. Furthermore, there is a special timing of the set latch pulse SL and a shunt bit line device T8 controlled by an associated signal SBL. Upon selection of the array, the bit lines are in a restored state from the preceding restore bit line RBL cycle. RBL is then turned off, while the set pulse at T7 is up from the preceding cycle. As a result, sense amplifier T1 to T4 is in a DC-stable state. As RBL is turned off, SL is set to 0 V, so that the sense amplifier is connected to bit lines BLT and BLC through T5 and T6, respectively. The additional pulse SBL is ...