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Browse Prior Art Database

Power-On Circuit

IP.com Disclosure Number: IPCOM000062128D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Barsness, R: AUTHOR [+4]

Abstract

A circuit is described by which current peaks, occurring during the power-on of DRAM (dynamic random-access memory) chips, are avoided. This eliminates overdimensioned power supplies and the provision of decoupling capacitors on circuit boards, as well as power sequencing. DRAM chips use the electric charge of small capacitors (cell capacitors) for storing data. In the off state (chip power off), these capacitors are discharged. However, when the supply voltage is switched on, they are abruptly charged in an uncontrolled manner, as the control signals have undefined levels in the absence of the full supply voltage.

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Power-On Circuit

A circuit is described by which current peaks, occurring during the power-on of DRAM (dynamic random-access memory) chips, are avoided. This eliminates overdimensioned power supplies and the provision of decoupling capacitors on circuit boards, as well as power sequencing. DRAM chips use the electric charge of small capacitors (cell capacitors) for storing data. In the off state (chip power off), these capacitors are discharged. However, when the supply voltage is switched on, they are abruptly charged in an uncontrolled manner, as the control signals have undefined levels in the absence of the full supply voltage. Because of the large number of cells on the chip, this abrupt charging of the storage capacitors leads to a very high current peak which is extremely undesirable and may be avoided by an overdimensioned power supply and additional capacitors on the circuit boards. As this approach is both cost- and space-consuming, it is uneconomical for small and medium-size systems. Power-on current peaks can be avoided if control signal -RASI of the memory follows the potential of supply voltage V5 during power-on. The circuit of Fig. 1, which is normally used to generate control signal -RASI, is insufficient for this purpose, as, during power- on, the push-pull driver temporarily switches its output level -RASI to down level. This is due to the fact that the input stage of the driver is driven at a low supply voltage V3 which is derived from supply voltage V5 applied to the chip, so that during power-on, V3 is below its nominal value. Thus, for a short time, control voltage -RASI does not follow supply voltage V5, leading to an undesired current peak. Fig. 2 shows the diagram of a circuit (power-on circuit) which pre...