Browse Prior Art Database

Functional Fault-Correction Method of Cache And/Or Directory Arrays

IP.com Disclosure Number: IPCOM000062129D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+3]

Abstract

In large chips, multiple word/bit redundancy techniques are used, at the chip level, in order to detect and correct faults in memory arrays. This technique consists of having spare decoders, words and bit lines in order to replace defective lines at these addresses. This type of redundancy technique can improve the chip yield, at the price of hardware overhead and performance penalty. The cost of that redundancy is estimated as a 10% overhead of that function's overall hardware, along with a performance degradation. In the case of a Cache system, this performance impact can pose a problem, since it impacts the machine's most critical timing machine cycle path.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 51% of the total text.

Page 1 of 3

Functional Fault-Correction Method of Cache And/Or Directory Arrays

In large chips, multiple word/bit redundancy techniques are used, at the chip level, in order to detect and correct faults in memory arrays. This technique consists of having spare decoders, words and bit lines in order to replace defective lines at these addresses. This type of redundancy technique can improve the chip yield, at the price of hardware overhead and performance penalty. The cost of that redundancy is estimated as a 10% overhead of that function's overall hardware, along with a performance degradation. In the case of a Cache system, this performance impact can pose a problem, since it impacts the machine's most critical timing machine cycle path. The amount of hardware spent in this redundancy technique, and performance impact, may not be cost effective, especially which considering clustered silicon defects on the Cache and/or Cache Directory arrays. In the present disclosure we propose a fault- coverage/correction method that is realized through functional Cache hardware. The advantage of this method, vis-a-vis another, is that it has negligible impact on the machine's critical timing path, and the hardware spent, for its realization, is cost effective for large clustered array defects. The term "functional" implies that the added hardware functions at the Cache system level. Any errors in the Cache and/or the Directory array can be corrected by providing hardware that functions as the original failing parts. The functional correction hardware is kept in minimum, with the least penalty in performance. A large number of faults can be covered and corrected, and thus improve the overall yield. During the initial testing, the addresses of the occurring faults in either the Cache and/or the Directory are placed into the Fail Address (FA) function, that is implemented with a read-only memory (ROM) (see figure). In the case of Cache faults, the data of the failing address is put, and operated from then on, in the Cache Line Buffer (CLB). Thus, any reference to that Cache Data Line is managed by that buffer. The FA ROM, contains the starting Cache Line Address or the Cache Directory Address, along with the particular compartment number, A, B, C or D, where the defects happened to occur. The number of bits necessary for the address depends on the number of congruence classes of that particular organization, along with two bits for the compartment, in the case of a four- way associative Cache design. The CLB consists of a random-access memory (RAM) where the contents of the Cache data lines are contained. The number of RAM bytes necessary depends on the Cache line size of the specific organization. For covering more defects than the defects of the particular Cache line, additional RAM will be required for the Cache Line Buffer. Any fault occurrence in the Cache array is marked in the ROM, the address of which is compared with the incoming CPU addresses. Any...