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Pseudo-Clock Generator to Prevent Data Loss in a Dynamic Memory

IP.com Disclosure Number: IPCOM000062130D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Malmquist, CA: AUTHOR [+2]

Abstract

A system containing an intelligent memory card that utilizes a signal sequencer for the control of the memory operation will experience an interruption in a memory operation in progress when the system clocks stop. When this happens, the memory control signals will not terminate properly. Also, the allow arbitration signal is prevented from going active, which stops the refresh signal from activating. This condition will cause data loss, not only in the memory card which was selected, but in all the memory cards. The generating of a set of pseudo clocks, using the storage clocks which run continuously, prevents this data loss, as described in the following. As seen in the timing diagram at point (A), a signal from the clock card is received indicating that the system clocks are going to stop.

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Pseudo-Clock Generator to Prevent Data Loss in a Dynamic Memory

A system containing an intelligent memory card that utilizes a signal sequencer for the control of the memory operation will experience an interruption in a memory operation in progress when the system clocks stop. When this happens, the memory control signals will not terminate properly. Also, the allow arbitration signal is prevented from going active, which stops the refresh signal from activating. This condition will cause data loss, not only in the memory card which was selected, but in all the memory cards. The generating of a set of pseudo clocks, using the storage clocks which run continuously, prevents this data loss, as described in the following. As seen in the timing diagram at point (A), a signal from the clock card is received indicating that the system clocks are going to stop. This signal when "ANDed" with the system TLAST (TL) will, if the storage controller is busy, cause the pseudo clocks to start (GEN P-CLOCKS). The storage send clock (STG SEND) (which occurs at system T0), is used to generate P0 and P2. The storage receive clock (which occurs at system T2) is used to generate P1 and PLAST . When the pseudo clocks are generated, the cycle time will double. To prevent the storage card from receiving two send and two receive clocks per cycle, the middle two storage clocks are blocked. This keeps the control signals in sync with the storage card. The storage controller and the storag...