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Very High Speed Adders With Cascode Differential Circuits

IP.com Disclosure Number: IPCOM000062132D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+2]

Abstract

Previously there was shown the excellent speed power product of the cascode circuits when compared to the traditional NAND gates in a master slice. This advantage is due to the fact that a complex function can be implemented in only one logic tree either with differential or single-ended circuits. The present disclosure describes an application with an Adder where the usage of the differential cascode circuit also gives a good speed power product. As an example, a 64-bit adder is described, with a sum which can be done in 4 cascode tree delays with 5 levels of bipolar or FET transistors. The design of a very high speed Adder - Subtractor is possible with the carry calculation made in a parallel mode in a look-ahead carry circuit. The table below is a truth table for the sum and the carry of 2 bits A and B with a carry in.

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Very High Speed Adders With Cascode Differential Circuits

Previously there was shown the excellent speed power product of the cascode circuits when compared to the traditional NAND gates in a master slice. This advantage is due to the fact that a complex function can be implemented in only one logic tree either with differential or single-ended circuits. The present disclosure describes an application with an Adder where the usage of the differential cascode circuit also gives a good speed power product. As an example, a 64-bit adder is described, with a sum which can be done in 4 cascode tree delays with 5 levels of bipolar or FET transistors. The design of a very high speed Adder - Subtractor is possible with the carry calculation made in a parallel mode in a look-ahead carry circuit. The table below is a truth table for the sum and the carry of 2 bits A and B with a carry in.

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The traditional logical equations with the minimum of product terms for the final sums of 2 numbers A and B are given below:

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For the carry part the formula can be general with the introduction of the terms: carry generate and propagate. Ai+Bi Propagate for bit i : Carry out = Carry in = 1 if Ai or Bi is at '1'. Ai Bi Generate for bit i : Forces carry out to 1 only if both Ai Bi are at '1'. A group of generate and a group of propagate (GGi and GPi) can be calculated from the lower weighted bits below index 'i'. GPi = P1 P2 ... Pi-1 GGi = (G1 P2 ... Pi-1)+(G2 P3 ... Pi-1)+ ... +(Gi-2 Pi-1)+Gi-1 With GPi and GGi the general formulation of the sum is: Si = Ai + Bi + (Cin GPi + GGi)
(1) The equation (1) can be modified to decrease the number of cascode levels needed to calculate a higher order of carry generate. We can see from the carry truth table that when the carry in is '0', the carry out is given by the generate, thus the equation can be modified to: Si = Ai + Bi + (Cin GPi + --- GGi) (2) The equation (2) gives an implementation of the tree which calculates the generate and the carry similarly to that described in the prior art. An alternate solution is to have the propagate equal to the XOR of Ai and Bi. In this case the Sum for 1 bit is: Si = Ai + Bi + (Cin Pj + Gj --) (3) with Pi = Ai + Bi and Gi = Ai Bi or GI = AI or GI = Bi j = i - 1 This equation can be generalized with groups of generate and propagate and gives an equation similar to (2). This last equation has been used to implement a full ADDER with a representation of the trees for carry propagate and generate as shown in Figs. 1, 2, 3, 4. Propagate for a group of 2 bits (Fig. 1; circuit type P2) The first calculation of pr...