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Interactive Integrated Circuit Design and Test System

IP.com Disclosure Number: IPCOM000062147D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Booker, G: AUTHOR [+7]

Abstract

A system is described which extends the use of existing automated circuit design, mask layout data, and circuit simulation of integrated circuits. Physical and electrical characteristics of an actual circuit are compared with characteristics derived from design and simulation. Actual electrical circuit characteristics are acquired from a stroboscopic electron beam tester (SEBT) integrated within this system. The interactive search, view, and test capability of the system is used in verification of new integrated circuit designs. The system provides ability to automatically check and verify electrical characteristics of actual devices with characteristics predicted by simulation and to subsequently flag and display any variances.

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Interactive Integrated Circuit Design and Test System

A system is described which extends the use of existing automated circuit design, mask layout data, and circuit simulation of integrated circuits. Physical and electrical characteristics of an actual circuit are compared with characteristics derived from design and simulation. Actual electrical circuit characteristics are acquired from a stroboscopic electron beam tester (SEBT) integrated within this system. The interactive search, view, and test capability of the system is used in verification of new integrated circuit designs. The system provides ability to automatically check and verify electrical characteristics of actual devices with characteristics predicted by simulation and to subsequently flag and display any variances. The block diagram indicates the interconnections and interaction of the commercially available components of which the system is comprised. Referring to the diagram, pattern generator 2 is hardware and software which generates all stimuli necessary for operation of a wide variety of integrated circuits. While testing an integrated circuit chip which is installed in SEBT 4, an appropriate set of stimuli are sent via cable from pattern generator 2 to the chip mounted to a stepper-driven stage in SEBT 4. Chip positioning, electron beam positioning and control are achieved by signals from minicomputer
8. Host system 6 provides data to minicomputer 8 from files generated in design of the circuit under test pertinent to chip positioning and SEBT 4 area scan control. System control is accomplished by operator input on keyboard 24 to host system 6. The operator is guided by observation of the circuit being generated on circuit schematic display 20 and two-dimensional physical layout being generated on graphical display 22. Design data is stored in files of the host system 6 and is available on demand from minicom...