Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Single-Centered Reading Amplifier

IP.com Disclosure Number: IPCOM000062157D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Coppens, P: AUTHOR [+4]

Abstract

This invention relates to a single-centered complementary metal-oxide- semiconductor (CMOS) sense amplifier to be used with a multiport random-access memory (RAM). The main feature of this sense amplifier is that it operates with a single bit line. Then it can be used to operate in conjunction with multiport RAMs provided with a cell having a single bit line at each port for reading. It can also operate with a cell provided with two bit lines while using only one. Description of operation The sense amplifier input is the node C, and point B is the output. 1.Pre-loading step Prior to each read or write operation, a pre-loading step to "1" is performed on the bit line by applying a "0" level on the clock input (---) of the sense amplifier.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

Single-Centered Reading Amplifier

This invention relates to a single-centered complementary metal-oxide- semiconductor (CMOS) sense amplifier to be used with a multiport random- access memory (RAM). The main feature of this sense amplifier is that it operates with a single bit line. Then it can be used to operate in conjunction with multiport RAMs provided with a cell having a single bit line at each port for reading. It can also operate with a cell provided with two bit lines while using only one. Description of operation The sense amplifier input is the node C, and point B is the output. 1.Pre-loading step Prior to each read or write operation, a pre- loading step to "1" is performed on the bit line by applying a "0" level on the clock input (---) of the sense amplifier. Thus there is a "1" at node D (due to the inversion) and a "1" at nodes C and B since T6 and T7 are conducting. As T4 is conducting, T1 and T2 are latched, maintaining a "1" at the output B, which is also restored to "1" through T7. Conclusion: on pre-loading, a "1" is outputted.
2.Reading operation A "1" is applied to the clock input (---). Transistors T6 and T7 are off, and a "0" at node D makes T5 conducting. Therefore, a "1" is at point
E. Reading a "0" A "0" applied to input C makes T3 conducting. Thus, a "1" at node A makes T2 conducting. Therefore, a "0" is at node B and T1 is conducting, maintaining node A at "1" and keeping T2 ON. The latching device, comprised of transistors T1 and T2...