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TWO-STEP ANNEALING PROCESS FOR GaAs MESFET FABRICATION

IP.com Disclosure Number: IPCOM000062173D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Nguyen, SV: AUTHOR [+4]

Abstract

This article describes an anneal process for GaAs MESFET fabrication which reduces Si3N4 film delamination caused by formation of blisters and bubbles on the wafer surface during Si3N4 capped anneal. The wafer is first annealed at a low temperature (preferably in the range of 400-600ŒC) in a conventional furnace to drive out hydrogen (and/or other) gases from the Si3N4 film. The wafer is then raised to a higher temperature, e.g., 800-1100ŒC for dopant activation and diffusion. This second anneal can be done either in a conventional furnace or by the rapid annealing method. Fig. 1 illustrates the bubbling and delamination problem associated with the conventional process. Fig. 2 illustrates the improvement obtained in the film surface by use of the two-step annealing process herein disclosed. In Fig.

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TWO-STEP ANNEALING PROCESS FOR GaAs MESFET FABRICATION

This article describes an anneal process for GaAs MESFET fabrication which reduces Si3N4 film delamination caused by formation of blisters and bubbles on the wafer surface during Si3N4 capped anneal. The wafer is first annealed at a low temperature (preferably in the range of 400-600OEC) in a conventional furnace to drive out hydrogen (and/or other) gases from the Si3N4 film. The wafer is then raised to a higher temperature, e.g., 800-1100OEC for dopant activation and diffusion. This second anneal can be done either in a conventional furnace or by the rapid annealing method. Fig. 1 illustrates the bubbling and delamination problem associated with the conventional process. Fig. 2 illustrates the improvement obtained in the film surface by use of the two- step annealing process herein disclosed. In Fig. 1, the sample shown was rapidly annealed at 1000OEC for two seconds. In Fig. 2, the sample shown was annealed by the present two-step annealing process involving a 650OEC furnace anneal in nitrogen gas for 60 minutes followed by a 1000OEC, 2-second rapid anneal. The extensive bubbling and delamination visible on the film surface of the Fig. 1 sample has been almost completely eliminated on the surface of the sample shown in Fig. 2., thereby contributing to a significant improvement in VLSI product yields.

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