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Bit Decoded Discharge Concept

IP.com Disclosure Number: IPCOM000062180D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Klein, W: AUTHOR [+4]

Abstract

A bit decoded discharge concept and a circuit array for its implementation are described which eliminate the previously required array chip discharge circuit and considerably improve the access time by providing a transistor diode TDIS between the bit reference line BRL and the collector of the bit driver transistor TBD. In addition, the value of the resistor (not shown) in the bit decoder is slightly reduced, so that transistor TBD is capable of additionally receiving the discharge current flowing on bit reference line BRL from the non- selected bit lines. The described concept is generally suitable for MTL (merged transistor logic) memory cells and is not limited to a particular embodiment of an MTL memory cell. The address and discharge step of a memory, comprising the bit decoded discharge concept, proceed as follows. 1.

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Bit Decoded Discharge Concept

A bit decoded discharge concept and a circuit array for its implementation are described which eliminate the previously required array chip discharge circuit and considerably improve the access time by providing a transistor diode TDIS between the bit reference line BRL and the collector of the bit driver transistor TBD. In addition, the value of the resistor (not shown) in the bit decoder is slightly reduced, so that transistor TBD is capable of additionally receiving the discharge current flowing on bit reference line BRL from the non- selected bit lines. The described concept is generally suitable for MTL (merged transistor logic) memory cells and is not limited to a particular embodiment of an MTL memory cell. The address and discharge step of a memory, comprising the bit decoded discharge concept, proceed as follows. 1. Lines BSW, associated with the unselected bit line pairs, remain at up level. The associated transistors TBS remain on. 2. The potential of line BSW, associated with a selected bit line, is lowered, initially switching off the bit switch transistors TBS through Schottky diode SBS. Bit lines B0, B1 subsequently float, retaining their stored charge. 3. If the potential of line BSW drops further, transistor TDIS is switched on, discharging bit reference line BRL to a potential at which the unselected bit lines are also discharged to that potential by transistors TBS. 4. Subsequently, the word line potential on word lines WL1, ..., WL128 is lowered, the selected bit lines B0, B1 being discharged according to the information stored in the memory cell (read operation) or a current, applied by write switches (not shown), determining the information to be stored in the memory cell (write operation). As the unselected bit lines B0, B1 are...