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Circuit to Solve Contention Problems Between Processor-Initiated Operations, Adapter-Initiated Operations and Interrupts on a Bus

IP.com Disclosure Number: IPCOM000062200D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Almairac, G: AUTHOR [+2]

Abstract

The circuit and method described in this article are to be used in a system comprising several adapters A connected to a processor P through a bus. They exchange information with processor P by means of PIOs (Processor-Initiated Operations) or by AIOs (Adapter-Initiated Operations). They can also raise interrupt lines to processor P to ask for a task. In such an environment, the circuit and method described below allow the contention problems to be solved. To perform a PIO, processor P takes the bus resource for transferring data to/from a selected adapter. To perform an AIO, the adapter takes the bus resource for transferring data to/from processor P. It initiates this operation by means of a channel request signal CHR. An interrupt is initiated by an adapter when there is no data transfer on the bus.

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Circuit to Solve Contention Problems Between Processor-Initiated Operations, Adapter-Initiated Operations and Interrupts on a Bus

The circuit and method described in this article are to be used in a system comprising several adapters A connected to a processor P through a bus. They exchange information with processor P by means of PIOs (Processor-Initiated Operations) or by AIOs (Adapter-Initiated Operations). They can also raise interrupt lines to processor P to ask for a task. In such an environment, the circuit and method described below allow the contention problems to be solved. To perform a PIO, processor P takes the bus resource for transferring data to/from a selected adapter. To perform an AIO, the adapter takes the bus resource for transferring data to/from processor P. It initiates this operation by means of a channel request signal CHR. An interrupt is initiated by an adapter when there is no data transfer on the bus. The adapter can change its interrupt request line which is a bit line of the data bus to ask the processor to change its task level. At that time, processor P must know if the interrupt request line was raised or dropped. As processor P is under microcode control, it must be warned by a hardware mechanism to start the microcode related to the request handling. Such a mechanism is shown in Fig. 1. Channel request lines CHRL are latched in the lowest part of re quest register REQR. If a channel request signal CHR appears, it raises the "start request handling microcode" latch L which warns processor P in order to start the request handling and stop the channel request and interrupt scanning on the bus. Interrupt lines are latched in register UCBR. Three bits are provided according to the three possible interrupt levels. A bit to bit comparison is made by comparator C1 with the three respective bits of the highest part of register REQR. An inequality means that an interrupt was raised or dropped. In this case latch L is set and UCBR register content is loaded into register REQR to drop the C1 output. Only the reset of latch L is done by microcode, the latches in registers REQR and UCBR being changed by the new bus lines status. The reset of latch L allows the scanning to be r...