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High Density Vertical DRAM Cell

IP.com Disclosure Number: IPCOM000062209D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Hwang, W: AUTHOR [+2]

Abstract

This article describes a new high density vertical trench DRAM (dynamic random-access memory) cell. The cross section of two adjacent DRAM cells is shown in Fig. 1 together with its schematic layout (Fig.2) and circuit diagram (Fig. 3). The transfer device is oriented in the vertical direction and is positioned over the trench storage capacitor. A shallow trench filled with polysilicon or polycide (e.g., poly-Si, WSi2, and Si) serves as the MOS transfer device gate. Transfer MOSFETs of adjacent cells share the same gate. Arrangement of the trench stor age capacitors and transfer devices are different from those of the conventional planar and trench DRAM cells. By placing the transfer device in a vertical orientation over the trench capacitor, cell area can be reduced. A cell layout is shown in Fig. 2.

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High Density Vertical DRAM Cell

This article describes a new high density vertical trench DRAM (dynamic random-access memory) cell. The cross section of two adjacent DRAM cells is shown in Fig. 1 together with its schematic layout (Fig.2) and circuit diagram (Fig.
3). The transfer device is oriented in the vertical direction and is positioned over the trench storage capacitor. A shallow trench filled with polysilicon or polycide (e.g., poly-Si, WSi2, and Si) serves as the MOS transfer device gate. Transfer MOSFETs of adjacent cells share the same gate. Arrangement of the trench stor age capacitors and transfer devices are different from those of the conventional planar and trench DRAM cells. By placing the transfer device in a vertical orientation over the trench capacitor, cell area can be reduced. A cell layout is shown in Fig. 2. A process sequence for vertical trench DRAM cells is as follows:
(1) On a wafer with p- epi on a p+ substrate, grow SiO2 (Fig. 4). (2) Define and etch deep trenches in the epitaxial substrate by using reactive-ion-etching (RIE) (Fig. 5). (3) Strip the silicon-dioxide film and regrown thin oxide/nitride composite insulating layer in the trench capacitor (Fig. 6). This is the storage capacitor insulator. (4) Fill the trench with chemical-vapor-deposition (CVD) n+ polysilcon film (Fig. 7). (5) Etch away the excess polysilicon not located above the two adjacent trenches using plasma etch (Fig. 8). (6) Thermally anneal the remaining polysilicon (by laser or tungsten lamp) to convert poly top layer to crystalline n+ layer (Fig. 9). (7) Regrow thick p-type epitaxial layer (Fig. 10). (8) Grow SiO2 and etch shallow trench (in epitaxial p-layer) between the trench capacitors using RIE (Fig. 11). (9) Implant oxygen (or nitrogen) below surface of new shallow trench to create isolation oxide at the bottom of the trench. Alternatively, a thin conformal layer of nitride can be dep...