Browse Prior Art Database

Sidewall Spacer Construction

IP.com Disclosure Number: IPCOM000062211D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Harame, DL: AUTHOR

Abstract

This article relates generally to integrated circuit fabrication and, more particularly, to a process for forming sidewall spacers. Non- conforming silicon evaporation and rapidly etched phosphorous glass enable more efficient and precise construction of bipolar devices. Referring to Fig. 1, nitride layer 1 is evaporated onto oxide layer 2 formed by a recessed oxide process on substrate 3. Boron phosphorous glass (BPSG) 4 is then evaporated onto the nitride layer in sufficient thickness for subsequent lift-off. Glass 4 is annealed and photoresist is deposited, exposed and developed to form the intrinsic base and emitter opening 5 with BPSG thereon. Reactive ion etching (RIE) removes the BPSG and nitride outside base and emitter region 5.

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Sidewall Spacer Construction

This article relates generally to integrated circuit fabrication and, more particularly, to a process for forming sidewall spacers. Non- conforming silicon evaporation and rapidly etched phosphorous glass enable more efficient and precise construction of bipolar devices. Referring to Fig. 1, nitride layer 1 is evaporated onto oxide layer 2 formed by a recessed oxide process on substrate
3. Boron phosphorous glass (BPSG) 4 is then evaporated onto the nitride layer in sufficient thickness for subsequent lift-off. Glass 4 is annealed and photoresist is deposited, exposed and developed to form the intrinsic base and emitter opening 5 with BPSG thereon. Reactive ion etching (RIE) removes the BPSG and nitride outside base and emitter region 5. Thereafter, silicon nitride is evaporated conformally at low temperature around BPSG 4 to form a cap preventing reflow of the previously annealed BPSG. The nitride may be annealed and is etched by RIE to leave sidewalls 6. In Fig. 2, polysilicon 7 is evaporated in a non-conformal manner. If 70% conformal, then an isotropic wet etch-back can be done to insure no coverage of sidewalls 6. Polysilicon thickness must compensate for future etching and oxidation stages. Polysilicon 7 is oxidized by layer 8 to a non-leaking thickness and annealed. Implantation of polysilicon 7 is done either before or after oxidation and more oxide is grown. Regions of the polysilicon outside the active base and emitter regio...