Browse Prior Art Database

External Register File for LSI Floating-Point Processors

IP.com Disclosure Number: IPCOM000062285D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Schumacher, DP: AUTHOR [+2]

Abstract

An arrangement is described in which a separate floating-point processor (FPP) is combined with a microprocessor. The trend in microprocessors is to implement floating-point arithmetic functions in a large-scale integrated (LSI) circuit separate from but closely coupled to the main processor. These FPP circuits were developed to provide a performance improvement over executing software in the main processor to implement the same function. Current technology does not permit the FPP and main processor to be combined in one LSI circuit. FPPs are usually slave processors to the main processor in a microprocessor-based system. They are issued commands and data by the main processor which are executed in lock step with it.

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External Register File for LSI Floating-Point Processors

An arrangement is described in which a separate floating-point processor (FPP) is combined with a microprocessor. The trend in microprocessors is to implement floating-point arithmetic functions in a large-scale integrated (LSI) circuit separate from but closely coupled to the main processor. These FPP circuits were developed to provide a performance improvement over executing software in the main processor to implement the same function. Current technology does not permit the FPP and main processor to be combined in one LSI circuit. FPPs are usually slave processors to the main processor in a microprocessor-based system. They are issued commands and data by the main processor which are executed in lock step with it. FPPs consist of several major logic groups: typically command interpretation/execution logic, a data input/output port, the arithmetic logic unit, and a data register file. Floating point operands are represented in binary computers as an ordered group of bits, usually from 24 to 80 bits. The size of the operands, the complexity of the FPP processing logic, and limits of current integrated circuit technology combine to limit the size of the register file in currently available FPPs to, typically, 8 registers. Fig. 1. is a block diagram of a typical microprocessor-based system. Fig. 2 is a block diagram of a typical floating-point processor. In order to load data into the FPP, the microprocessor first loads it from system memory to one of its registers and then transfers it to the FPP's register file. These accesses take several times longer than the register file to FPP's ALU (arithmetic logic unit) transfers. In the typical FPP diagram, the dotted line connecting the I/O port directly to the ALU allows the FPP...