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High Performance Complementary Decoder/Driver Circuit

IP.com Disclosure Number: IPCOM000062287D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Chappell, BA: AUTHOR [+2]

Abstract

This article describes a circuit using complementary devices that is useful as a wordline decoder and driver in a RAM (random-access memory) or for similar logical functions. Some advantages of this circuit are: No DC power is needed, power is dissipated only during switching and minimal delay is exhibited because only two-stage delays are included, one for decoding and one for driving. Also, there are minimal timing delays because there is no clocking after the address lines have switched. There is minimal loading on the inputs because only one device per input is needed with no ratioing required.

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High Performance Complementary Decoder/Driver Circuit

This article describes a circuit using complementary devices that is useful as a wordline decoder and driver in a RAM (random-access memory) or for similar logical functions. Some advantages of this circuit are: No DC power is needed, power is dissipated only during switching and minimal delay is exhibited because only two-stage delays are included, one for decoding and one for driving. Also, there are minimal timing delays because there is no clocking after the address lines have switched. There is minimal loading on the inputs because only one device per input is needed with no ratioing required. There is minimal loading on the clock inputs because no DC current is supplied by clock inputs, small device count and an addition, only five devices plus one device per input are necessary for operation, and dynamic storage time on internal nodes is minimal and well controlled. A system approach that considers the decoder circuits in pairs is used to achieve these features, as shown in Fig. l, using CMOS devices. Waveforms describing the circuit operation as wordline decoders/drivers are given in Fig. 2. The waveforms label the sequential states that would occur for two access conditions and for the reset and precharge states that occur after an access, during every RAM cycle. The states are also described in the table in Fig. 2. This publication will describe the basic operation of the circuit, followed by a discussion of design requirements for proper operation, and possible modifications to assure that second-order effects, such as coupling and leakage of precharged highs, are not problems. Fig. 2 begins with the precharge state (labeled state "A") wherein the precharge clock (PC) is low and the decoder inputs (the address lines and the reset clock (R)) are also low. This state of the inputs allows every "a" node (ai---aj) to charge to VDD through device 7i---7j and every "b" node to be high due to retained charge from the previous access (as will be seen from the subsequent description). As a consequence of the "b" node being high, the wordline is clamped low through the inverting driver stage (devices l and 2). Before the next cycle and the address lines rising, the PC input is taken high, cutting off device 7. When a RAM access occurs, there are two possible cases to be considered, since the decoder circuits are designed in pairs. Fig. 2 illustrates first the case (state "B") wherein one decoder (decoder "i" in Fig. l) is selected and the other (decoder "j") is not. This case will occur if all of the address lines connected to the decoder "i" inputs stay low and if at least one of the address lines connected to decoder "j" goes high. (At this time, the PC input is high and the R input is low.) The result of this input state is that node "ai" stays high, while node "aj" is discharged to ground, thereby providing a discharge path for node "bi" through devices 4i and 5j (or one o...