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Buffer Amplifier With Ultra-Low Output Impedance

IP.com Disclosure Number: IPCOM000062307D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 32K

Publishing Venue

IBM

Related People

Chesters, MJ: AUTHOR [+2]

Abstract

In a buffer amplifier, two NPN transistors are connected in long tail pair configuration with collector currents reflected in a unity gain PNP current mirror. Two further NPN transistors are connected in cascode configuration to form a high gain output structure with based currents supplied by opposite sides of the unity gain PNP current mirror. The balanced base currents of the output transistors, with the output structure connected into a negative feedback configuration, guarantee ultra-low output impedance. As shown in the diagram, the circuit comprises a long tail pair input structure T1 and T2, a high gain output structure T3 and T4, and a high efficiency unity ratio PNP mirror structure T5, T6 and T7. The output of the buffer amplifier may be required to sink current as well as source current.

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Buffer Amplifier With Ultra-Low Output Impedance

In a buffer amplifier, two NPN transistors are connected in long tail pair configuration with collector currents reflected in a unity gain PNP current mirror. Two further NPN transistors are connected in cascode configuration to form a high gain output structure with based currents supplied by opposite sides of the unity gain PNP current mirror. The balanced base currents of the output transistors, with the output structure connected into a negative feedback configuration, guarantee ultra-low output impedance. As shown in the diagram, the circuit comprises a long tail pair input structure T1 and T2, a high gain output structure T3 and T4, and a high efficiency unity ratio PNP mirror structure T5, T6 and T7. The output of the buffer amplifier may be required to sink current as well as source current. For this reason, a standing current, Ist, is connected to the output node. The circuit output current is therefore Iout-Ist, which may be positive or negative. Ist does not affect the operation of the circuit. The base current of T1 is supplied by the input. The base current of T2 is supplied by the emitter current of T3. I1 is the current applied to the emitters of T1 and T2. The PNP mirror structure mirrors the collector current of T1 and the base current of T4 into the T2 collector and T3 base node. At equilibrium, Vout = Vin and, therefore, transistors T1 and T2 conduct the same current (0.5 x I1). If Vout were to fall below Vin, then the collector current of T2 would fall and the collector current of T1 would rise. The increase in T1 collector current would be reflected in the PNP mirror as a similar increase in T6 collector current, and since this current would be greater than T2 collector current, the excess current would be applied to the base of T3. The emitter current of T3 would increase and, with it, T2 base current and voltage would increase, causing T2 collector current to increase. This would have the twin effect of reducing T1 collector current and T3 base current. Equilibrium would therefore be re-established. If Vout were to rise above Vin, equilibrium would similarly be re-established. Therefore, the circuit maintains the equilibrium state of Vout = Vin,...