Browse Prior Art Database

Microprocessor Buffer Caching

IP.com Disclosure Number: IPCOM000062313D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Hughes, DR: AUTHOR [+3]

Abstract

This article describes an apparatus and method for processing data generated from terminals connected to a loop communications network. A single shared buffer is used to store data from the terminals. The shared buffer is normally controlled by a dedicated microprocessor. The dedicated microprocessor periodically allows the main processor to access the buffer. During the intervals when the main processor is accessing the shared buffer, a cache memory which may be internal to the dedicated microprocessor is used for storing data from the terminals. The figure shows the caching operation for two processors sharing a single buffer. The legends at the right hand side of the diagram identify the components and/or action taken at a particular instant of time.

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Microprocessor Buffer Caching

This article describes an apparatus and method for processing data generated from terminals connected to a loop communications network. A single shared buffer is used to store data from the terminals. The shared buffer is normally controlled by a dedicated microprocessor. The dedicated microprocessor periodically allows the main processor to access the buffer. During the intervals when the main processor is accessing the shared buffer, a cache memory which may be internal to the dedicated microprocessor is used for storing data from the terminals. The figure shows the caching operation for two processors sharing a single buffer. The legends at the right hand side of the diagram identify the components and/or action taken at a particular instant of time. Likewise, the numerals at the bottom of the figure indicate the actions taken at a specific instant of time. Thus, at Interval #1: the shared buffer controller which may be an 8051 microprocessor pulls the received data off the loop and places it in the shared buffer, then interrupts the main microprocessor. Interval #2: while the main microprocessor is removing message A from the shared buffer, the 8051 is caching message B and starts caching message C. Interval #3: the main microprocessor returns the shared buffer and the 8051 loads the cache into it and the rest of message C. Interval #4: the main microprocessor moves message B and C while the 8051 is caching the beginning of messa...