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Memory Testing With Linear Feedback Shift Register

IP.com Disclosure Number: IPCOM000062326D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Hubbard, PJ: AUTHOR

Abstract

Diagnostic testing is disclosed for a system having two or more RAMs (random-access memories) each connected to a data bus together with a parallel input linear feedback shift register (LFSR). Test data is fed to a first RAM, and when this data block is transferred to a second RAM, the LFSR monitors and compresses the data into a unique signature. If this signature is correct, the second RAM data is transferred to a third RAM to be checked in the same way. At present, for the power-on-self-test used with the PC systems, the operator can be asked to wait for several minutes whilst the system checks through and verifies its RAM, among other things. The method currently used is to write specified test patterns to memory blocks that test for stuck bits, etc.

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Memory Testing With Linear Feedback Shift Register

Diagnostic testing is disclosed for a system having two or more RAMs (random- access memories) each connected to a data bus together with a parallel input linear feedback shift register (LFSR). Test data is fed to a first RAM, and when this data block is transferred to a second RAM, the LFSR monitors and compresses the data into a unique signature. If this signature is correct, the second RAM data is transferred to a third RAM to be checked in the same way. At present, for the power-on-self-test used with the PC systems, the operator can be asked to wait for several minutes whilst the system checks through and verifies its RAM, among other things. The method currently used is to write specified test patterns to memory blocks that test for stuck bits, etc. Each byte is then read back and compared with a known good byte to ensure data integrity, a new byte of test data being written in its place. The technique proposed here will drastically reduce this test time by the implementation of a simple piece of hardware, namely a LFSR with multiple inputs. This would be positioned in such a way so as to enable data bus monitoring, as in the drawing. At memory test initialization, the parallel input LFSR is set so as to monitor and read data from the data bus. RAM 1 can be filled with a test pattern and block transferred to RAM 2. The LFSR will create from this data on the bus, via data compression, a unique signature that...