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Dynamically Reconfigurable Microprocessing System

IP.com Disclosure Number: IPCOM000062350D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Bahnsen, RJ: AUTHOR [+6]

Abstract

Several activities in the area of design automation (DA) can exploit parallel processing using low cost microprocessors. What is needed is a system that will: exploit parallelism within an architecture for the partitioning of engineering design data and algorithms, and adjust and modify the logical machine configuration to the algorithm being run to optimize performance. This is highly dependent upon the method of processor intercommunication. One of the fundamental problems when using parallel processing is the communication between the processors. Having an interconnection network that matches the problem to be solved or the algorithm to be solved increases efficiency and machine performance.

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Dynamically Reconfigurable Microprocessing System

Several activities in the area of design automation (DA) can exploit parallel processing using low cost microprocessors. What is needed is a system that will: exploit parallelism within an architecture for the partitioning of engineering design data and algorithms, and adjust and modify the logical machine configuration to the algorithm being run to optimize performance. This is highly dependent upon the method of processor intercommunication. One of the fundamental problems when using parallel processing is the communication between the processors. Having an interconnection network that matches the problem to be solved or the algorithm to be solved increases efficiency and machine performance. To delineate between hardware structure and different logical configurations that can be obtained from such structure, two concepts or definitions are useful: Physical Configuration - is the way a particular collection of hardware is interconnected. In other words, the relationships between physical entities such as microprocessors, busses, memories and I/O devices are described by the physical configuration. Logical Configuration - describes a mapping of memory and processors that is suitable for solving a particular problem utilizing a specific algorithm. Note that several mappings of memories and processors can be associated with one problem when that problem is solved by different algorithms. Fig. 1 shows the physical architecture of a parallel processing system capable of being formed into a plurality of logical configurations. An executive processor 10 is connected to a global bus 11 to which is connected a plurality of cells 12 and a global buffer 13. Processor 10 is connected also to a memory 14 and to a host system and/or a workstation (not shown). Each cell has a bimodal memory 16 (Fig. 2) connected between global bus 11 and a cell bus 18 to which are connected a plurality of microprocessor cards 20.

Each card also includes local random-access memory and read-only memory. Executive processor 10 is a general-purpose microcomputer having the following functions: 1. Data interface to host computer. 2. Connection to a workstation to provide the user interface. 3. Global bus 11 arbitration. 4. Configuration control.
5. Data transfer to and from all memories. 6. Configuration diagnostics. 7. Control of access to each bimodal memory 16. Global buffer 13 has the following functions: 1. Inter-cell communication. 2. S...