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Polysilicon Deposition Process

IP.com Disclosure Number: IPCOM000062356D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

This article relates generally to integrated circuit fabrication and, more particularly, to deposition of multiple layers of polysilicon. The application of an oxide layer to a polysilicon gate by chemical vapor deposition followed by reactive ion etching enables better profile control and support of the second polysilicon layer. In Fig. 1, gate oxide formation 1 on silicon substrate 2 includes deposition of polysilicon layer 3 covered by oxide layer 4 that is deposited by chemical vapor deposition. This stack is photolithographically defined and anisotropically etched to form the gate. Another oxide layer 5 is then deposited by chemical vapor deposition in Fig. 2. Reactive ion etching removes the deposited oxide 5, but forms sidewalls 6, as in Fig. 3.

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Polysilicon Deposition Process

This article relates generally to integrated circuit fabrication and, more particularly, to deposition of multiple layers of polysilicon. The application of an oxide layer to a polysilicon gate by chemical vapor deposition followed by reactive ion etching enables better profile control and support of the second polysilicon layer. In Fig. 1, gate oxide formation 1 on silicon substrate 2 includes deposition of polysilicon layer 3 covered by oxide layer 4 that is deposited by chemical vapor deposition. This stack is photolithographically defined and anisotropically etched to form the gate. Another oxide layer 5 is then deposited by chemical vapor deposition in Fig. 2. Reactive ion etching removes the deposited oxide 5, but forms sidewalls 6, as in Fig. 3. Thereafter, conventional processing is used to apply the second polysilicon layer. In this processing, the slope of sidewalls or spacers 6 is a function of the oxide thickness deposited in Fig. 2. An increasing thickness produces a steeper sidewall after etching. Sidewall formation more easily facilitates the slope of the second polysilicon deposition and insures its integrity.

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